34 lines
922 B
Verilog
34 lines
922 B
Verilog
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// Insert tlast bit for fifos that don't support it. This only works with VALID CVITA frames
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// A single partial or invalid frame will make this wrong FOREVER
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module cvita_insert_tlast
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(input clk, input reset, input clear,
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input [63:0] i_tdata, input i_tvalid, output i_tready,
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output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready);
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assign o_tdata = i_tdata;
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assign o_tvalid = i_tvalid;
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assign i_tready = o_tready;
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wire [15:0] cvita_len_ceil = i_tdata[47:32] + 7;
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wire [15:0] axi_len = {3'b000, cvita_len_ceil[15:3]};
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reg [15:0] count;
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assign o_tlast = (count != 0) ? (count == 16'd1) : (axi_len == 16'd1);
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always @(posedge clk)
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if(reset | clear)
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begin
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count <= 16'd0;
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end
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else
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if(i_tready & i_tvalid)
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if(count != 16'd0)
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count <= count - 16'd1;
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else
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count <= axi_len - 16'd1;
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endmodule // cvita_insert_tlast
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