adf6f576c6
FPGA: - Split up MB registers that control daughterboard specific settings so that daughterboards 0 and 1 could have different setings, in preparation for future devices that require different settings. This requires a compat number bump to 8.0. - Add registers for additional RFDC information, including the block/tile mapping of the individual channels, and information about resampling capabilities - Identify sections of code that would be specific to X410/ZBX and move them to their own headers, so it's trivial to add device-specific sections of code instead for other devices in the future. - This includes constraints for clocks and I/O pins. - Remove ability to do timed ctrlport transactions to the MB CPLD, this was unused and possibly broken. - Move daughterboard-specific code into its own code location (dboards/zbx) - Move X410-specific register documentation to its own location (doc/X410) - Refactor Makefiles to split out X410/ZBX specific components and allow switching between device types - Add 512-bit AXI interconnects - Make number of timekeepers configurable (X410 keeps the single timekeeper) MPM: - Required compat is bumped to 8.0 - Now supports new registers for detecting DSP capabilities and multi-rate settings for the daughterboards - Adds MMCM controls (currently unused) Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
33 lines
1.1 KiB
Makefile
33 lines
1.1 KiB
Makefile
#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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include $(TOOLS_DIR)/make/viv_ip_builder.mak
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IP_AXI_INTER_1X512_512_ORIG_SRCS = $(addprefix $(IP_DIR)/axi_inter_1x512_512_bd/, \
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axi_inter_1x512_512_bd.tcl \
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)
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IP_AXI_INTER_1X512_512_BDTCL_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_1x512_512_bd/, \
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axi_inter_1x512_512_bd.tcl \
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)
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IP_AXI_INTER_1X512_512_BD_SRCS = $(addprefix $(IP_BUILD_DIR)/axi_inter_1x512_512_bd/, \
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axi_inter_1x512_512_bd/axi_inter_1x512_512_bd.bd \
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)
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BD_AXI_INTER_1X512_512_BD_OUTS = $(addprefix $(IP_BUILD_DIR)/axi_inter_1x512_512_bd/, \
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axi_inter_1x512_512_bd.bd.out \
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axi_inter_1x512_512_bd/axi_inter_1x512_512_bd_ooc.xdc \
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axi_inter_1x512_512_bd/synth/axi_inter_1x512_512_bd.v \
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)
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.INTERMEDIATE: IP_AXI_INTER_1X512_512_BD_TRGT
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$(IP_AXI_INTER_1X512_512_BD_SRCS) $(BD_AXI_INTER_1X512_512_BD_OUTS) $(IP_AXI_INTER_1X512_512_BDTCL_SRCS): IP_AXI_INTER_1X512_512_BD_TRGT
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@:
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IP_AXI_INTER_1X512_512_BD_TRGT: $(IP_AXI_INTER_1X512_512_ORIG_SRCS)
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$(call BUILD_VIVADO_BDTCL,axi_inter_1x512_512_bd,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),$(LIB_DIR)/vivado_ipi)
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