185 lines
7.2 KiB
Makefile
185 lines
7.2 KiB
Makefile
#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
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##-------------------
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##USRP X4xx FPGA Help
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##-------------------
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##Usage:
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## make <Targets> <Options>
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##
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##Output:
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## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header
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## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.dts: Device tree source file
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## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary)
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# Base output directory for all builds.
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BUILD_BASE_DIR ?= .
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# Base directory for the build outputs.
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BUILD_OUTPUT_DIR ?= $(BUILD_BASE_DIR)/build
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# Sane defaults for IP builds
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X410_IP: DEFS += QSFP0_0=2 RF_BW=100
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X440_IP: DEFS += QSFP0_0=2 RF_BW=400
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# DRAM IP inclusion. Set to 1 to include DRAM memory controller in design, 0 to
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# exclude it. Note that some targets exclude it regardless of this setting.
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DRAM ?= 1
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IMAGE_CORE_NAME ?= usrp_fpga
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DEFS += $(OPTIONS)
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# Initialize a build seed. This can be changed to randomly affect build results.
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BUILD_SEED ?= 0
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DEFS += BUILD_SEED=$(BUILD_SEED)
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# Default value for incremental Vivado build is disabled.
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INCR_BUILD ?= 0
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# Option to stop after RTL elaboration. Use this flag as a synthesis check.
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ifndef TARGET
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ifeq ($(CHECK), 1)
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TARGET = rtl
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else ifeq ($(SYNTH), 1)
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TARGET = synth
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else ifeq ($(IP_ONLY), 1)
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TARGET = viv_ip
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else ifeq ($(SECURE_CORE), 1)
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TARGET = secure_core
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TOP = secure_image_core
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else
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TARGET = bin
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endif
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endif
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TOP ?= x4xx
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ifdef ARTIFACT_DIR
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BUILD_DIR = $(ARTIFACT_DIR)
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endif
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# vivado_build($1=Device (X410 or X440), $2=Definitions)
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vivado_build = make -f Makefile.x4xx.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) EXTRA_DEFS="$2" TOP_MODULE=$(TOP) $2 INCR_BUILD=$(INCR_BUILD)
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vivado_ip = make -f Makefile.x4xx.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) EXTRA_DEFS="$2" TOP_MODULE=$(TOP) $2
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# vivado_build($1=Device)
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ifeq ($(TARGET),bin)
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post_build = @\
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mkdir -p $(BUILD_OUTPUT_DIR); \
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echo "Exporting bitstream file..."; \
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cp $(ARTIFACT_DIR)/x4xx.bit $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bit; \
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echo "Exporting build report..."; \
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cp $(ARTIFACT_DIR)/build.rpt $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).rpt; \
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echo "Build DONE ... $(IMAGE_CORE_NAME)";
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else
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post_build = @echo "Skipping bitfile export."
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endif
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##
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##Available Targets
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##-------------|-----------|----|-----------------|-----------------|------------
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##Target | Bandwidth | Ch | QSFP0 | QSFP1 | DRAM
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##-------------|-----------|----|-----------------|-----------------|------------
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##X410_X1_100 | 100 MHz | 4 | 10 GbE (Lane 0) | Unused | 64b x 4 Ch
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##X410_XG_100 | 100 MHz | 4 | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
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##X410_X4_100 | 100 MHz | 4 | 4 x 10 GbE | Unused | 64b x 4 Ch
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##X410_X4C_100 | 100 MHz | 4 | 4 x 10 GbE | 100 GbE | Unused
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##X410_C1_100 | 100 MHz | 4 | 100 GbE | Unused | 64b x 4 Ch
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##X410_UC_100 | 100 MHz | 4 | Unused | 100 GbE | 64b x 4 Ch
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##X410_X1_200 | 200 MHz | 4 | 10 GbE (Lane 0) | Unused | 64b x 4 Ch
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##X410_XG_200 | 200 MHz | 4 | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 64b x 4 Ch
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##X410_X4_200 | 200 MHz | 4 | 4 x 10 GbE | Unused | 64b x 4 Ch
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##X410_X4C_200 | 200 MHz | 4 | 4 x 10 GbE | 100 GbE | Unused
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##X410_C1_200 | 200 MHz | 4 | 100 GbE | Unused | 64b x 4 Ch
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##X410_UC_200 | 200 MHz | 4 | Unused | 100 GbE | 64b x 4 Ch
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##X410_X1_400 | 400 MHz | 4 | 10 GbE (Lane 0) | Unused | 128b x 4 Ch
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##X410_XG_400 | 400 MHz | 4 | 10 GbE (Lane 0) | 10 GbE (Lane 0) | 128b x 4 ch
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##X410_X4_400 | 400 MHz | 4 | 4 x 10 GbE | Unused | 128b x 4 Ch
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##X410_C1_400 | 400 MHz | 4 | 100 GbE | Unused | Unused
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##X410_UC_400 | 400 MHz | 4 | Unused | 100 GbE | Unused
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##X410_CG_400 | 400 MHz | 4 | 100 GbE | 100 GbE | Unused
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##X440_X1_400 | 400 MHz | 8 | 10 GbE (Lane 0) | Unused | 128b x 8 Ch
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##X440_X4_400 | 400 MHz | 8 | 4 x 10 GbE | Unused | 128b x 8 Ch
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##X440_C1_400 | 400 MHz | 8 | 100 GbE | Unused | Unused
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##X440_CG_400 | 400 MHz | 8 | 100 GbE | 100 GbE | Unused
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##X440_X1_1600 | 1.6 GHz | 2 | 10 GbE (Lane 0) | Unused | 512b x 2 Ch
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##X440_X4_1600 | 1.6 GHz | 2 | 4 x 10 GbE | Unused | 512b x 2 Ch
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##X440_C1_1600 | 1.6 GHz | 2 | 100 GbE | Unused | Unused
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##X440_CG_1600 | 1.6 GHz | 2 | 100 GbE | 100 GbE | Unused
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##* Note: Not all targets are shipped with UHD
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##* Note: Some YAML configurations might not use all available DRAM channels.
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X410: X410_IP build/$(IMAGE_CORE_NAME).dts
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$(call vivado_build,X410,$(DEFS) X410=1)
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$(call post_build,X410)
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X440: X440_IP build/$(IMAGE_CORE_NAME).dts
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$(call vivado_build,X440,$(DEFS) X440=1)
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$(call post_build,X440)
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##
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##Other Make Targets
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##------------------
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.DEFAULT_GOAL := all
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all: X410_IP
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X410_IP: ##Build X410 IP only.
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+$(call vivado_ip,X410,$(DEFS) X410=1)
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X440_IP: ##Build X440 IP only.
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+$(call vivado_ip,X440,$(DEFS) X440=1)
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$(BUILD_OUTPUT_DIR)/usrp_x410%.dts: dts/*.dts dts/*.dtsi
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-mkdir -p $(BUILD_OUTPUT_DIR)
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tools/parse_versions_for_dts.py \
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--input regmap/x410/versioning_regs_regmap_utils.vh \
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--output dts/x410-version-info.dtsi \
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--components fpga,cpld_ifc,db_gpio_ifc,rf_core_100m,rf_core_400m
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${CC} -o $@ -C -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ \
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$(ARTIFACT_DIR)/device_tree.dts
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$(BUILD_OUTPUT_DIR)/usrp_x440%.dts: dts/*.dts dts/*.dtsi
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-mkdir -p $(BUILD_OUTPUT_DIR)
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tools/parse_versions_for_dts.py \
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--input regmap/x440/versioning_regs_regmap_utils.vh \
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--output dts/x440-version-info.dtsi \
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--components fpga,cpld_ifc,db_gpio_ifc,rf_core_full
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${CC} -o $@ -C -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ \
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$(ARTIFACT_DIR)/device_tree.dts
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clean: ##Clean up all target build outputs.
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@echo "Cleaning targets..."
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@rm -rf $(BUILD_BASE_DIR)/build-X* $(BUILD_BASE_DIR)/build-x*
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@rm -rf $(BUILD_OUTPUT_DIR)
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cleanall: ##Clean up all target and IP build outputs.
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@echo "Cleaning targets and IP..."
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@rm -rf build-ip
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@rm -rf $(BUILD_BASE_DIR)/build-*
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@rm -rf $(BUILD_OUTPUT_DIR)
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help: ##Show this help message.
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@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
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##
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##Supported Options
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##-----------------
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##INCR_BUILD=0 Use incremental Vivado build to speed up consecutive runs
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##GUI=1 Launch the build in the Vivado GUI.
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##PROJECT=1 Save Vivado project file, otherwise it's created in memory.
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##CHECK=1 Launch the syntax checker instead of building a bitfile.
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##IP_ONLY=1 Launch the build but stop after IP generation.
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##SYNTH=1 Launch the build but stop after synthesis.
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##SECURE_CORE=1 Launch a build of the secure image core only.
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##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0)
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##TOP=<module> Specify a top module for syntax checking. (Default is the bitfile top)
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.PHONY: all clean cleanall help
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