91 lines
2.7 KiB
Makefile
91 lines
2.7 KiB
Makefile
#
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# Copyright 2015 Ettus Research LLC
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../..)
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# Include viv_sim_preample after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Define part using PART_ID (<device>/<package>/<speedgrade>)
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ARCH = kintex7
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PART_ID = xc7k410t/ffg900/-2
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# Include makefiles and sources for the DUT and its dependencies
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include $(BASE_DIR)/../lib/fifo/Makefile.srcs
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include $(BASE_DIR)/../lib/axi/Makefile.srcs
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include $(BASE_DIR)/../lib/control/Makefile.srcs
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DESIGN_SRCS = $(abspath \
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$(FIFO_SRCS) \
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$(AXI_SRCS) \
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$(CONTROL_LIB_SRCS) \
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)
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#-------------------------------------------------
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# IP Specific
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#-------------------------------------------------
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# If simulation contains IP, define the IP_DIR and point
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# it to the base level IP directory
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IP_DIR = ../../ip
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# Include makefiles and sources for all IP components
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# *after* defining the IP_DIR
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include $(IP_DIR)/ddr3_32bit/Makefile.inc
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include $(IP_DIR)/axi_intercon_2x64_128_bd/Makefile.inc
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include $(IP_DIR)/fifo_short_2clk/Makefile.inc
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include $(IP_DIR)/fifo_4k_2clk/Makefile.inc
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include $(IP_DIR)/axi4_dualport_sram/Makefile.inc
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DESIGN_SRCS += $(abspath \
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$(IP_DDR3_32BIT_SRCS) \
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$(IP_AXI_INTERCON_2X64_128_SRCS) \
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$(IP_AXI_INTERCON_2X64_128_BD_SRCS) \
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$(IP_FIFO_4K_2CLK_SRCS) \
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$(IP_FIFO_SHORT_2CLK_SRCS) \
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$(IP_AXI4_BRAM_SRCS) \
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)
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#-------------------------------------------------
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# ModelSim Specific
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#-------------------------------------------------
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MODELSIM_IP_SRCS = $(wildcard $(abspath \
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$(IP_BUILD_DIR)/fifo_short_2clk/sim/fifo_short_2clk.v \
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$(IP_BUILD_DIR)/axi4_dualport_sram/sim/axi4_dualport_sram.v \
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$(VIVADO_PATH)/data/verilog/src/glbl.v \
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))
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MODELSIM_LIBS += \
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fifo_generator_v13_2_4 \
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blk_mem_gen_v8_4_3 \
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modelsim vlint : SIM_SRCS += $(MODELSIM_IP_SRCS)
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MODELSIM_ARGS += glbl -t 1fs
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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# Define only one top-level module
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SIM_TOP = dram_fifo_bist_tb
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SIM_SRCS += \
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$(abspath dram_fifo_bist_tb.sv) \
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$(abspath ../dram_fifo/axis_dram_fifo_single.sv) \
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$(IP_DDR3_32BIT_SIM_OUTS) \
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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