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Martin BraunAlex WilliamsAndrej RodeAshish ChaudhariBen HilburnCiro NishiguchiDaniel JepsonDerek KozelEJ KreinarHumberto JimenezIan BuckleyJörg HofrichterJon KiserJosh BlumJonathon PendlumMatt EttusMichael WestMoritz FischerNick FosterNicolas CuervoPaul ButlerPaul DavidRyan MarlowSugandha GuptaSylvain MunautTrung TranVidush VishwanathWade Fife
6b67702ad7
Martin BraunAlex WilliamsAndrej RodeAshish ChaudhariBen HilburnCiro NishiguchiDaniel JepsonDerek KozelEJ KreinarHumberto JimenezIan BuckleyJörg HofrichterJon KiserJosh BlumJonathon PendlumMatt EttusMichael WestMoritz FischerNick FosterNicolas CuervoPaul ButlerPaul DavidRyan MarlowSugandha GuptaSylvain MunautTrung TranVidush VishwanathWade FifeThe FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
205 lines
6.0 KiB
Verilog
205 lines
6.0 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "generic_fifo.v" ////
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//// ////
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//// This file is part of the "10GE MAC" project ////
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//// http://www.opencores.org/cores/xge_mac/ ////
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//// ////
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//// Author(s): ////
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//// - A. Tanguay (antanguay@opencores.org) ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 AUTHORS. All rights reserved. ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`include "defines.v"
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module generic_fifo(
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wclk,
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wrst_n,
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wen,
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wdata,
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wfull,
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walmost_full,
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rclk,
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rrst_n,
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ren,
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rdata,
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rempty,
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ralmost_empty
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);
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//---
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// Parameters
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parameter DWIDTH = 32;
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parameter AWIDTH = 3;
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parameter RAM_DEPTH = (1 << AWIDTH);
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parameter SYNC_WRITE = 1;
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parameter SYNC_READ = 1;
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parameter REGISTER_READ = 0;
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parameter EARLY_READ = 0;
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parameter CLOCK_CROSSING = 1;
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parameter ALMOST_EMPTY_THRESH = 1;
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parameter ALMOST_FULL_THRESH = RAM_DEPTH-2;
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parameter MEM_TYPE = `MEM_AUTO_SMALL;
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//---
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// Ports
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input wclk;
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input wrst_n;
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input wen;
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input [DWIDTH-1:0] wdata;
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output wfull;
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output walmost_full;
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input rclk;
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input rrst_n;
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input ren;
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output [DWIDTH-1:0] rdata;
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output rempty;
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output ralmost_empty;
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// Wires
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wire mem_wen;
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wire [AWIDTH:0] mem_waddr;
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wire mem_ren;
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wire [AWIDTH:0] mem_raddr;
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generic_fifo_ctrl #(.AWIDTH (AWIDTH),
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.RAM_DEPTH (RAM_DEPTH),
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.EARLY_READ (EARLY_READ),
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.CLOCK_CROSSING (CLOCK_CROSSING),
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.ALMOST_EMPTY_THRESH (ALMOST_EMPTY_THRESH),
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.ALMOST_FULL_THRESH (ALMOST_FULL_THRESH)
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)
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ctrl0(.wclk (wclk),
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.wrst_n (wrst_n),
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.wen (wen),
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.wfull (wfull),
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.walmost_full (walmost_full),
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.mem_wen (mem_wen),
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.mem_waddr (mem_waddr),
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.rclk (rclk),
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.rrst_n (rrst_n),
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.ren (ren),
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.rempty (rempty),
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.ralmost_empty (ralmost_empty),
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.mem_ren (mem_ren),
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.mem_raddr (mem_raddr)
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);
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generate
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if (MEM_TYPE == `MEM_AUTO_SMALL) begin
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generic_mem_small #(.DWIDTH (DWIDTH),
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.AWIDTH (AWIDTH),
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.RAM_DEPTH (RAM_DEPTH),
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.SYNC_WRITE (SYNC_WRITE),
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.SYNC_READ (SYNC_READ),
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.REGISTER_READ (REGISTER_READ)
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)
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mem0(.wclk (wclk),
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.wrst_n (wrst_n),
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.wen (mem_wen),
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.waddr (mem_waddr),
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.wdata (wdata),
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.rclk (rclk),
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.rrst_n (rrst_n),
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.ren (mem_ren),
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.roen (ren),
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.raddr (mem_raddr),
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.rdata (rdata)
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);
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end
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if (MEM_TYPE == `MEM_AUTO_MEDIUM) begin
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generic_mem_medium #(.DWIDTH (DWIDTH),
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.AWIDTH (AWIDTH),
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.RAM_DEPTH (RAM_DEPTH),
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.SYNC_WRITE (SYNC_WRITE),
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.SYNC_READ (SYNC_READ),
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.REGISTER_READ (REGISTER_READ)
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)
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mem0(.wclk (wclk),
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.wrst_n (wrst_n),
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.wen (mem_wen),
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.waddr (mem_waddr),
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.wdata (wdata),
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.rclk (rclk),
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.rrst_n (rrst_n),
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.ren (mem_ren),
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.roen (ren),
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.raddr (mem_raddr),
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.rdata (rdata)
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);
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end // if (MEM_TYPE == `MEM_AUTO_MEDIUM)
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if (MEM_TYPE == `MEM_AUTO_XILINX) begin
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generic_mem_xilinx_block #(.DWIDTH (DWIDTH),
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.AWIDTH (AWIDTH),
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.RAM_DEPTH (RAM_DEPTH),
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.SYNC_WRITE (SYNC_WRITE),
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.SYNC_READ (SYNC_READ),
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.REGISTER_READ (REGISTER_READ)
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)
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mem0(.wclk (wclk),
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.wrst_n (wrst_n),
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.wen (mem_wen),
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.waddr (mem_waddr),
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.wdata (wdata),
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.rclk (rclk),
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.rrst_n (rrst_n),
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.ren (mem_ren),
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.roen (ren),
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.raddr (mem_raddr),
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.rdata (rdata)
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);
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end
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endgenerate
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endmodule
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