Wade Fife
4f99fee248
The underlying Xilinx CORDIC IP uses 2 bits for the whole part of its (X,Y) inputs and its magnitude output. So, having 17 bits means we have enough precision to represent the entire range of an sc16. The 16-bit CORDIC is insufficient to cover this entire range. Original-commit: 0d3d69493aac9239ae437b04f291c61669678606
22 lines
838 B
Makefile
22 lines
838 B
Makefile
#
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# Copyright 2024 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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include $(TOOLS_DIR)/make/viv_ip_builder.mak
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LIB_IP_COMPLEX_TO_MAGPHASE_INT17_SRCS = $(IP_BUILD_DIR)/complex_to_magphase_int17/complex_to_magphase_int17.xci
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LIB_IP_COMPLEX_TO_MAGPHASE_INT17_OUTS = $(addprefix $(IP_BUILD_DIR)/complex_to_magphase_int17/, \
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complex_to_magphase_int17.xci.out \
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synth/complex_to_magphase_int17.vhd \
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)
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.INTERMEDIATE: LIB_IP_COMPLEX_TO_MAGPHASE_INT17_TRGT
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$(LIB_IP_COMPLEX_TO_MAGPHASE_INT17_SRCS) $(LIB_IP_COMPLEX_TO_MAGPHASE_INT17_OUTS): LIB_IP_COMPLEX_TO_MAGPHASE_INT17_TRGT
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@:
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LIB_IP_COMPLEX_TO_MAGPHASE_INT17_TRGT: $(LIB_IP_DIR)/complex_to_magphase_int17/complex_to_magphase_int17.xci
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$(call BUILD_VIVADO_IP,complex_to_magphase_int17,$(ARCH),$(PART_ID),$(LIB_IP_DIR),$(IP_BUILD_DIR),0)
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