70 lines
1.3 KiB
Verilog
70 lines
1.3 KiB
Verilog
module float_to_iq_tb();
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reg clk, reset;
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integer x,file;
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reg [31:0] in;
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wire [15:0] out;
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initial clk = 0;
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always #10 clk = ~clk;
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initial $dumpfile("float_to_iq_tb.vcd");
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initial $dumpvars(0,float_to_iq_tb);
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initial
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begin
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x <= 0;
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reset <= 1;
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in <= 0;
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file = $fopen("float_to_iq_VER.txt");
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repeat(65536) @(posedge clk);
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reset <=0;
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repeat(65536) @(posedge clk)
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begin
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in <= data[x];
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x <= x+1;
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$fdisplayh(file,out);
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end
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$fclose(file);
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repeat(65536) @(posedge clk);
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$finish;
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end
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float_to_iq #(.BITS_IN(32),.BITS_OUT(16))
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dut
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(
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.in(in), .out(out), .clk(clk), .reset(reset)
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);
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//input
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reg [31:0] data [0:65535];
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initial $readmemh("iq_to_float_output.txt",data);
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//golden output
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//
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/*
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reg [15:0] out_array [0:65535];
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initial $readmemh("my_data.txt",out_array);
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reg fail;
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initial
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fail <= 0;
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//compare golden output with your output
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always @(posedge clk) begin
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if (out != out_array[index]) begin
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$display("Line %d : Expected %x, got %x",index,out_array[index],out);
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fail <= 1;
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end
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end
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*/
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end
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endmodule
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