c91b74de336864ebef6980eef97f6c5a23eca954
Original-commit: 0df4b801a34697f2058b4a7b95e08d2a0576c9db
The file is empty.
Languages
Verilog
42.5%
VHDL
13%
SystemVerilog
12%
HTML
11.1%
C
9.6%
Other
11.6%