33 lines
688 B
Verilog
33 lines
688 B
Verilog
// -*- verilog -*-
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//
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// USRP - Universal Software Radio Peripheral
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//
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// Copyright (C) 2008 Matt Ettus
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//
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//
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// Rounding "macro"
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// Keeps the topmost bits, does proper 2s comp rounding (round-to-zero)
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module round_reg
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#(parameter bits_in=0,
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parameter bits_out=0)
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(input clk,
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input [bits_in-1:0] in,
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output reg [bits_out-1:0] out,
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output reg [bits_in-bits_out:0] err);
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wire [bits_out-1:0] temp;
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wire [bits_in-bits_out:0] err_temp;
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round #(.bits_in(bits_in),.bits_out(bits_out)) round (.in(in),.out(temp), .err(err_temp));
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always @(posedge clk)
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out <= temp;
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always @(posedge clk)
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err <= err_temp;
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endmodule // round_reg
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