22 lines
402 B
Verilog
22 lines
402 B
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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module add2_and_round_reg
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#(parameter WIDTH=16)
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(input clk,
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input [WIDTH-1:0] in1,
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input [WIDTH-1:0] in2,
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output reg [WIDTH-1:0] sum);
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wire [WIDTH-1:0] sum_int;
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add2_and_round #(.WIDTH(WIDTH)) add2_n_rnd (.in1(in1),.in2(in2),.sum(sum_int));
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always @(posedge clk)
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sum <= sum_int;
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endmodule // add2_and_round_reg
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