96 lines
3.4 KiB
Makefile
96 lines
3.4 KiB
Makefile
#
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# Copyright 2012 Ettus Research LLC
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#
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##################################################
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# Coregen Sources
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##################################################
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CG_TMP_DIR = $(HOME)/.tmp/$(NAME)_coregen
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CG_SOURCE_DIR = $(BASE_DIR)/x300/coregen
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CG_BUILD_DIR = $(BUILD_DIR)/coregen
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COREGEN_SRCS = $(abspath $(addprefix $(CG_BUILD_DIR)/, \
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input_sample_fifo.v \
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input_sample_fifo.xco \
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axi64_8k_2clk_fifo.v \
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fifo_4k_2clk.v \
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radio_clk_gen.v \
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radio_clk_gen.xco \
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bus_clk_gen.v \
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bus_clk_gen.xco \
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pcie_clk_gen.v \
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pcie_clk_gen.xco \
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bootram.xco \
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))
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COREGEN_DRAM_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \
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axi_intercon_2x64_128.xco \
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ddr3_32bit/user_design/rtl/ddr3_32bit.v \
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ddr3_32bit/user_design/constraints/ddr3_32bit.ucf \
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ddr3_32bit.xco \
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))
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COREGEN_CHIPSCOPE_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \
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chipscope_ila.v \
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chipscope_ila.xco \
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chipscope_ila_64.v \
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chipscope_ila_64.xco \
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chipscope_icon.v \
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chipscope_icon.xco \
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chipscope_icon_2port.v \
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chipscope_icon_2port.xco \
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fifo_xlnx_16x40_2clk.v \
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fifo_xlnx_16x40_2clk.xco \
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fifo_short_2clk.v \
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fifo_short_2clk.xco \
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))
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ONE_GIG_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \
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gige_sfp_mdio.v \
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gige_sfp_mdio/example_design/gige_sfp_mdio_block.v \
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gige_sfp_mdio/example_design/gige_sfp_mdio_reset_sync.v \
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gige_sfp_mdio/example_design/gige_sfp_mdio_sync_block.v \
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gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_transceiver.v \
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gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_gtwizard.v \
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gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_gtwizard_gt.v \
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gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_gtwizard_init.v \
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gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_tx_startup_fsm.v \
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gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_rx_startup_fsm.v \
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gige_sfp_mdio/example_design/transceiver/gige_sfp_mdio_recclk_monitor.v \
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gige_sfp.v \
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gige_sfp/example_design/gige_sfp_block.v \
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gige_sfp/example_design/gige_sfp_reset_sync.v \
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gige_sfp/example_design/gige_sfp_sync_block.v \
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gige_sfp/example_design/transceiver/gige_sfp_transceiver.v \
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gige_sfp/example_design/transceiver/gige_sfp_gtwizard.v \
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gige_sfp/example_design/transceiver/gige_sfp_gtwizard_gt.v \
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gige_sfp/example_design/transceiver/gige_sfp_gtwizard_init.v \
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gige_sfp/example_design/transceiver/gige_sfp_tx_startup_fsm.v \
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gige_sfp/example_design/transceiver/gige_sfp_rx_startup_fsm.v \
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))
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TEN_GIG_SRCS = $(abspath $(addprefix $(CG_SOURCE_DIR)/, \
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ten_gig_eth_pcs_pma.v \
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ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.v \
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ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_x300_top.ucf \
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ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_block.v \
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ten_gig_eth_pcs_pma/example_design/ten_gig_eth_pcs_pma_mod.v \
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ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gt_usrclk_source.v \
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ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser_gt.v \
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ten_gig_eth_pcs_pma/example_design/gtx/ten_gig_eth_pcs_pma_gtwizard_10gbaser.v \
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))
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#make rule to regenerate bootram when the coe file is changed
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#this takes place out of tree to make the coregen tool happy
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$(CG_TMP_DIR)/bootram.coe: $(CG_SOURCE_DIR)/bootram.coe
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mkdir -p $(CG_TMP_DIR)
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cp -r $(CG_SOURCE_DIR)/* $(CG_TMP_DIR)/
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coregen -b $(CG_TMP_DIR)/bootram.xco -p $(CG_TMP_DIR) -r
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#copy all coregen products into the build dir
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#these products will be deleted with make clean
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$(COREGEN_SRCS): $(CG_TMP_DIR)/bootram.coe
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mkdir -p $(CG_BUILD_DIR)
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cp -r $(CG_SOURCE_DIR)/* $(CG_BUILD_DIR)/
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cp -r $(CG_TMP_DIR)/bootram.* $(CG_BUILD_DIR)/
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