96 lines
2.8 KiB
Verilog
96 lines
2.8 KiB
Verilog
//////////////////////////////////////////////////////////////////////////////////
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// Copyright Ettus Research LLC
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// The ZYNQ FIFO slave settings:
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// - implements write state machine for 32-bit addressable AXI slave
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// - provides settings for state of per-stream fifo pointers
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// - implements configuration of FIFO's physical DDR addresses
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//////////////////////////////////////////////////////////////////////////////////
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module zf_slave_settings
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#(
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parameter CONFIG_BASE = 32'h40000000
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)
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(
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input clk,
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input rst,
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//------------------------------------------------------------------
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//-- control write signals - slave
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//------------------------------------------------------------------
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input [31:0] AXI_AWADDR,
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input AXI_AWVALID,
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output AXI_AWREADY,
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input [31:0] AXI_WDATA,
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input [3:0] AXI_WSTRB,
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input AXI_WVALID,
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output AXI_WREADY,
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output [1:0] AXI_BRESP,
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output AXI_BVALID,
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input AXI_BREADY,
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//------------------------------------------------------------------
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// settings interface
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//------------------------------------------------------------------
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output reg [31:0] addr,
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output reg [31:0] data,
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output strobe,
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output [31:0] debug
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);
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////////////////////////////////////////////////////////////////////////
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///////////////////////////// Begin R T L //////////////////////////////
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////////////////////////////////////////////////////////////////////////
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//------------------------------------------------------------------
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// Control write state machine responds to AXI control writes
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// Used for setting the state of the various FIFOs
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//------------------------------------------------------------------
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localparam STATE_ADDR = 0;
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localparam STATE_DATA = 1;
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localparam STATE_WRITE = 2;
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reg [1:0] state;
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always @(posedge clk) begin
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if (rst) begin
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state <= STATE_ADDR;
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addr <= 0;
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data <= 0;
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end
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else case (state)
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STATE_ADDR: begin
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if (AXI_AWVALID && AXI_AWREADY) begin
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addr <= (AXI_AWADDR - CONFIG_BASE);
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state <= STATE_DATA;
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end
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end
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STATE_DATA: begin
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if (AXI_WVALID && AXI_WREADY) begin
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data <= AXI_WDATA;
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state <= STATE_WRITE;
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end
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end
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STATE_WRITE: begin
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state <= STATE_ADDR;
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end
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default: state <= STATE_ADDR;
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endcase //state
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end
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assign strobe = (state == STATE_WRITE);
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//assign to slave write
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assign AXI_AWREADY = (state == STATE_ADDR);
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assign AXI_WREADY = (state == STATE_DATA);
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assign AXI_BRESP = 0;
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assign AXI_BVALID = AXI_BREADY; //FIXME - we can choose not to assert valid
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endmodule //zf_slave_settings
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