50 lines
1.5 KiB
Verilog
50 lines
1.5 KiB
Verilog
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module axi64_to_ll8
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#(parameter START_BYTE=6)
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(input clk, input reset, input clear,
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input [63:0] axi64_tdata, input axi64_tlast, input [3:0] axi64_tuser, input axi64_tvalid, output axi64_tready,
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output [7:0] ll_data, output ll_eof, output ll_src_rdy, input ll_dst_rdy);
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reg [7:0] data_int;
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wire eof_int, valid_int, ready_int;
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reg [2:0] state = START_BYTE;
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reg eof, done;
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reg [3:0] occ;
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always @(posedge clk)
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if(reset | clear)
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state <= START_BYTE;
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else
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if(valid_int & ready_int)
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if(eof_int)
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state <= START_BYTE;
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else
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state <= state + 3'd1;
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assign valid_int = axi64_tvalid;
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assign axi64_tready = ready_int & (eof_int | state == 7);
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assign eof_int = axi64_tlast & (axi64_tuser[2:0] == (state + 3'd1));
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always @*
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case(state)
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0 : data_int <= axi64_tdata[63:56];
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1 : data_int <= axi64_tdata[55:48];
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2 : data_int <= axi64_tdata[47:40];
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3 : data_int <= axi64_tdata[39:32];
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4 : data_int <= axi64_tdata[31:24];
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5 : data_int <= axi64_tdata[23:16];
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6 : data_int <= axi64_tdata[15:8];
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7 : data_int <= axi64_tdata[7:0];
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default : data_int <= axi64_tdata[7:0];
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endcase // case (state)
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axi_fifo_short #(.WIDTH(9)) ll8_fifo
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(.clk(clk), .reset(reset), .clear(0),
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.i_tdata({eof_int, data_int}), .i_tvalid(valid_int), .i_tready(ready_int),
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.o_tdata({ll_eof, ll_data}), .o_tvalid(ll_src_rdy), .o_tready(ll_dst_rdy),
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.space(), .occupied());
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endmodule // axi64_to_ll8
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