157 lines
6.4 KiB
Verilog
157 lines
6.4 KiB
Verilog
//
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// Copyright 2013 Ettus Research LLC
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//
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`define BIT_WIDTH(N) (\
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N <= 2 ? 1 : \
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N <= 4 ? 2 : \
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N <= 8 ? 3 : \
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N <= 16 ? 4 : \
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N <= 32 ? 5 : \
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N <= 64 ? 6 : \
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N <= 128 ? 7 : \
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N <= 256 ? 8 : \
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N <= 512 ? 9 : \
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10)
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`define GET_REG_OFFSET(reg_addr, chan_idx) (((chan_idx * (1<<DMA_REG_GRP_W)) + reg_addr) + REG_BASE_ADDR)
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`define EXTRACT_CHAN_NUM(reg_addr) regi_addr[`BIT_WIDTH(NUM_STREAMS)+DMA_REG_GRP_W-1:DMA_REG_GRP_W]
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module pcie_dma_ctrl #(
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parameter NUM_STREAMS = 4,
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parameter FRAME_SIZE_W = 16,
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parameter REG_BASE_ADDR = 20'h00000,
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parameter ENABLE_ROUTER = 0,
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parameter ROUTER_SID_W = 8,
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parameter ROUTER_DST_W = 2
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) (
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input clk,
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input reset,
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input [63:0] regi_tdata,
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input regi_tvalid,
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output regi_tready,
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output [63:0] rego_tdata,
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output rego_tvalid,
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input rego_tready,
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output reg [NUM_STREAMS-1:0] set_clear,
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output [(NUM_STREAMS*FRAME_SIZE_W)-1:0] set_frame_size,
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output [(NUM_STREAMS*3)-1:0] swap_lanes,
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input [NUM_STREAMS-1:0] packet_stb,
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input [NUM_STREAMS-1:0] sample_stb,
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input [NUM_STREAMS-1:0] stream_err,
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input [ROUTER_SID_W-1:0] rtr_sid,
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output [ROUTER_DST_W-1:0] rtr_dst
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);
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localparam DMA_REG_GRP_W = 4;
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localparam DMA_CTRL_STATUS_REG = 4'h0; //[RW] R: Stream Error, W: Reset stream
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localparam DMA_FSIZE_REG = 4'h4; //[RW] R: Frame Size, W: Frame Size
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localparam DMA_SAMP_CNT_REG = 4'h8; //[RW] R: Sample Count, W: Reset Count to 0
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localparam DMA_PKT_CNT_REG = 4'hC; //[RW] R: Packet Count, W: Reset Count to 0
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localparam DEFAULT_FSIZE = 32;
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//NOTE: Although this module supports these, the 8 and 16 bit modes will be disabled for efficiency
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localparam DMA_CTRL_BUF_SIZE_8 = 2'b00; // 8-bit wide SW buffer
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localparam DMA_CTRL_BUF_SIZE_16 = 2'b01; //16-bit wide SW buffer
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localparam DMA_CTRL_BUF_SIZE_32 = 2'b10; //32-bit wide SW buffer
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localparam DMA_CTRL_BUF_SIZE_64 = 2'b11; //64-bit wide SW buffer
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wire regi_wr, regi_rd;
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wire [19:0] regi_addr;
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wire [31:0] regi_payload;
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wire [31:0] rego_payload;
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ioport2_msg_decode regi_decoder (
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.message(regi_tdata), .wr_request(regi_wr), .rd_request(regi_rd),
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.address(regi_addr), .data(regi_payload)
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);
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ioport2_msg_encode rego_encoder (
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.rd_response(1'b1), .data(rego_payload), .message(rego_tdata)
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);
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reg [31:0] pkt_count_mem[0:NUM_STREAMS-1];
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reg [31:0] samp_count_mem[0:NUM_STREAMS-1];
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reg [FRAME_SIZE_W-1:0] frame_size_mem[0:NUM_STREAMS-1];
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reg [NUM_STREAMS-1:0] sw_buf_width_mem;
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genvar i;
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generate
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for (i=0; i<NUM_STREAMS; i=i+1) begin: dma_ctrl_logic_generator
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//Memory -> output translations
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assign set_frame_size[(FRAME_SIZE_W*(i+1))-1:(FRAME_SIZE_W*i)] = frame_size_mem[i];
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assign swap_lanes[(3*(i+1))-1:(3*i)] = { ~(sw_buf_width_mem[i]), 2'b00 }; //Optimized for only 2 modes
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//Setting registers
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always @(posedge clk) begin
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if (reset) begin
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frame_size_mem[i] <= DEFAULT_FSIZE;
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set_clear[i] <= 0;
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sw_buf_width_mem[i] <= 1;
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end else if (regi_tready & regi_tvalid & regi_wr) begin
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if (regi_addr == `GET_REG_OFFSET(DMA_CTRL_STATUS_REG, i)) begin
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set_clear[i] <= regi_payload[0]; //DMA_CTRL_STATUS_REG[0] == Clear DMA queues
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sw_buf_width_mem[i] <= regi_payload[4]; //DMA_CTRL_STATUS_REG[5:4] == SW Buffer Size (See note above)
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end else if (regi_addr == `GET_REG_OFFSET(DMA_FSIZE_REG, i)) begin
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frame_size_mem[i] <= regi_payload[FRAME_SIZE_W-1:0]; //DMA_FSIZE_REG[14:0] == DMA Frame size
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set_clear[i] <= 1;
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end
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end else begin
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set_clear[i] <= 0; //set_clear should be "self-clearing"
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end
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end
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//Packet counter
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always @(posedge clk) begin
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if (reset | (regi_tvalid && regi_wr && (regi_addr == `GET_REG_OFFSET(DMA_PKT_CNT_REG, i)))) begin
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pkt_count_mem[i] <= 0;
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end else if (packet_stb[i]) begin
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pkt_count_mem[i] <= pkt_count_mem[i] + 1;
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end
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end
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//Sample counter
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always @(posedge clk) begin
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if (reset | (regi_tvalid && regi_wr && (regi_addr == `GET_REG_OFFSET(DMA_SAMP_CNT_REG, i)))) begin
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samp_count_mem[i] <= 0;
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end else if (sample_stb[i]) begin
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samp_count_mem[i] <= samp_count_mem[i] + 1;
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end
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end
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end
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endgenerate
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//Readback
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assign rego_payload =
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(regi_addr[DMA_REG_GRP_W-1:0] == DMA_PKT_CNT_REG) ? pkt_count_mem[`EXTRACT_CHAN_NUM(regi_addr)] : (
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(regi_addr[DMA_REG_GRP_W-1:0] == DMA_SAMP_CNT_REG) ? samp_count_mem[`EXTRACT_CHAN_NUM(regi_addr)] : (
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(regi_addr[DMA_REG_GRP_W-1:0] == DMA_FSIZE_REG) ? frame_size_mem[`EXTRACT_CHAN_NUM(regi_addr)] : (
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(regi_addr[DMA_REG_GRP_W-1:0] == DMA_CTRL_STATUS_REG) ? {31'h0, stream_err[`EXTRACT_CHAN_NUM(regi_addr)]} : (
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32'hFFFFFFFF))));
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assign rego_tvalid = regi_tvalid && regi_rd;
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assign regi_tready = rego_tready || (regi_tvalid && regi_wr);
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//Optional router
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if (ENABLE_ROUTER == 1) begin
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pcie_pkt_route_specifier #(
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.BASE_ADDR((1<<ROUTER_SID_W) + REG_BASE_ADDR), .ADDR_MASK(20'hFFFFF^((1<<ROUTER_SID_W)-1)),
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.SID_WIDTH(ROUTER_SID_W), .DST_WIDTH(ROUTER_DST_W)
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) route_specifier (
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.clk(clk), .reset(reset),
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.regi_tdata(regi_tdata), .regi_tvalid(regi_tvalid), .regi_tready(),
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.local_sid(rtr_sid), .fifo_dst(rtr_dst)
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);
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end
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endmodule
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`undef EXTRACT_CHAN_NUM
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`undef GET_REG_OFFSET
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`undef BIT_WIDTH
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