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Wade Fife fcfc6bf387 fpga: Update testbenches to work in ModelSim 
Original-commit: 0076076467303247c4e62e5824e5bf8ce79cbe66
2021-06-17 08:16:59 -05:00
..
coregen_dsp
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ip
x300: Expand DRAM address space to 1G
2020-05-18 17:50:38 -05:00
sim
fpga: Update testbenches to work in ModelSim
2021-06-17 08:16:59 -05:00
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build_x300.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
bus_int.v
fpga: Update DRAM IO signatures
2020-09-03 15:26:33 -05:00
capture_ddrlvds.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dev_config.json
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
gen_ddrlvds.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile.x300.inc
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
nirio_chdr64_adapter.v
fpga: remove liberio
2020-07-20 16:01:03 -05:00
setupenv.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
soft_ctrl.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
timing.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x3x0_base.lvbitx
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_1ge.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_10ge_port0.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_10ge_port1.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_10ge.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_aurora.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_core.v
fpga: Update DRAM IO signatures
2020-09-03 15:26:33 -05:00
x300_dram.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_eth_interface.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_pcie_int.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_rfnoc_image_core.v
fpga: Update rfnoc_image_core for all targets
2021-06-10 11:56:58 -05:00
x300_rfnoc_image_core.vh
fpga: Update rfnoc_image_core for all targets
2021-06-10 11:56:58 -05:00
x300_rfnoc_image_core.yml
fpga: Change RFNoC YAML version numbers to strings
2021-06-08 15:48:59 -05:00
x300_sfpp_io_core.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_static_router.hex
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
x300_zpu_config.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x310_rfnoc_image_core.v
fpga: Update rfnoc_image_core for all targets
2021-06-10 11:56:58 -05:00
x310_rfnoc_image_core.vh
fpga: Update rfnoc_image_core for all targets
2021-06-10 11:56:58 -05:00
x310_rfnoc_image_core.yml
fpga: Change RFNoC YAML version numbers to strings
2021-06-08 15:48:59 -05:00
x310_static_router.hex
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00