5cadf901c7
Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
36 lines
1.1 KiB
Verilog
36 lines
1.1 KiB
Verilog
//
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// Copyright 2022 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: x440_rfdc_tx_control_remap.v
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// Description:
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// Allows for remapping control signals to the correct tile on X440.
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// This file targets the DAC tiles specifically
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//
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`default_nettype none
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module x440_rfdc_tx_control_remap (
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// Input control (Front-Panel ordering)
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input wire [7:0] input_controls,
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// output_control (DAC Tile ordering)
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output wire [7:0] output_controls
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);
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`include "../../regmap/x440/rfdc_mapping_regmap_utils.vh"
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// Decode TX Channel mapping
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assign output_controls[CH0_TX_MAPPING] = input_controls[0];
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assign output_controls[CH1_TX_MAPPING] = input_controls[1];
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assign output_controls[CH2_TX_MAPPING] = input_controls[2];
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assign output_controls[CH3_TX_MAPPING] = input_controls[3];
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assign output_controls[CH4_TX_MAPPING] = input_controls[4];
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assign output_controls[CH5_TX_MAPPING] = input_controls[5];
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assign output_controls[CH6_TX_MAPPING] = input_controls[6];
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assign output_controls[CH7_TX_MAPPING] = input_controls[7];
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endmodule
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`default_nettype wire
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