mschill
4ae2f8eb5e
Together with an update to the LMK04832 register config according to TIs data sheet, all clock outputs are now aligned to SYSREF rising edge. Therefore, I needed to adjust the SYSREF capture mechanism inside the RFSoC and the SYSREF LMK Delay. SYSREF is now captured first at the falling edge of PRC. To be on the safe side, we are still double synchronizing SYSREF afterwards on the rising edges of PRC. As we are now independent of any MCR regarding timing constraints the SYSREF Delay is also set to '0' for all X4xx devices. Original-commit: b5cb4fac42ab530174e108455b730ffa1510d70a
77 lines
2.5 KiB
Verilog
77 lines
2.5 KiB
Verilog
//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: capture_sysref
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//
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// Description:
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//
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// Capture SYSREF and transfer it to the higher clock domain.
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// For X410, module incurs in 2 pll_ref_clk cycles + 1 rfdc_clk
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// cycle of delay. For X440, module synchronizes to each
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// pll_ref_clk and rfdc_clk separately, incurring in 2 cycles
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// for each clock.
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//
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// Parameters:
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//
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// DEVICE_TYPE : Type of device for which SYSREF is synchronized.
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//
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module capture_sysref (
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// Clocks
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input wire pll_ref_clk,
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input wire rfdc_clk,
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// SYSREF input and control
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input wire sysref_in, // Single-ended SYSREF (previously buffered)
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input wire enable_rclk, // Enables SYSREF output in the rfdc_clk domain.
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// Captured SYSREF outputs
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output wire sysref_out_pclk, // Debug output (Domain: pll_ref_clk).
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output wire sysref_out_rclk // RFDC output (Domain: rfdc_clk).
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);
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(* ASYNC_REG = "TRUE" *) reg sysref_neg_pclk_ms = 1'b0;
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(* ASYNC_REG = "TRUE" *) reg sysref_pos_pclk_ms = 1'b0;
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reg sysref_pclk = 1'b0;
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reg sysref_rclk = 1'b0;
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// The following waveform illustrates the capture process of SYSREF.
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//
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// PRC ___/-----\_____/-----\_____/-----\_____/----
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// SYSREF ___/----------------------------------------
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// falling edge FF MS ---------|R|--------------------------------
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// rising edge FF MS ---------------|R|--------------------------
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// rising edge FF ---------------------------|R|--------------
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//
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// Capture SYSREF synchronously with the pll_ref_clk, but at the falling edge.
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// This is done to ensure that SYSREF is captured well after its initial
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// rising edge to ensure a stable signal.
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// But to be on the safe side when combining this FPGA code with older
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// LMK04832 MPM configuration (before June 2024), the signal is considered
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// metastable and requires additional double synchronization.
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always @ (negedge pll_ref_clk) begin
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sysref_neg_pclk_ms <= sysref_in;
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end
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always @ (posedge pll_ref_clk) begin
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sysref_pos_pclk_ms <= sysref_neg_pclk_ms;
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sysref_pclk <= sysref_pos_pclk_ms;
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end
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assign sysref_out_pclk = sysref_pclk;
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// Transfer to faster clock which is edge-aligned with the pll_ref_clk.
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always @ (posedge rfdc_clk) begin
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if (enable_rclk) begin
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sysref_rclk <= sysref_pclk;
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end else begin
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sysref_rclk <= 1'b0;
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end
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end
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assign sysref_out_rclk = sysref_rclk;
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endmodule
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