Sam O'Brien
1b952d33df
Commit includes: - Upgrade x400-specific IP - Removal of xge_pcs_pma IP patch Original-commit: e94deac2efb8c3167eb2d70a385a8fa0ad657b55
356 lines
14 KiB
Tcl
356 lines
14 KiB
Tcl
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################################################################
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# This is a generated script based on design: eth_100g_bd
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#
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# Though there are limitations about the generated script,
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# the main purpose of this utility is to make learning
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# IP Integrator Tcl commands easier.
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################################################################
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namespace eval _tcl {
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proc get_script_folder {} {
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set script_path [file normalize [info script]]
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set script_folder [file dirname $script_path]
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return $script_folder
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}
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}
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variable script_folder
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set script_folder [_tcl::get_script_folder]
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################################################################
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# Check if script is running in correct Vivado version.
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################################################################
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set scripts_vivado_version 2021.1
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set current_vivado_version [version -short]
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if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
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puts ""
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catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
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return 1
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}
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################################################################
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# START
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################################################################
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# To test this script, run the following commands from Vivado Tcl console:
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# source eth_100g_bd_script.tcl
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# If there is no project opened, this script will create a
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# project, but make sure you do not have an existing project
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# <./myproj/project_1.xpr> in the current working folder.
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set list_projs [get_projects -quiet]
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if { $list_projs eq "" } {
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create_project project_1 myproj -part xczu28dr-ffvg1517-1-e
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}
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# CHANGE DESIGN NAME HERE
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variable design_name
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set design_name eth_100g_bd
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# If you do not already have an existing IP Integrator design open,
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# you can create a design using the following command:
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# create_bd_design $design_name
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# Creating design if needed
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set errMsg ""
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set nRet 0
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set cur_design [current_bd_design -quiet]
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set list_cells [get_bd_cells -quiet]
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if { ${design_name} eq "" } {
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# USE CASES:
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# 1) Design_name not set
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set errMsg "Please set the variable <design_name> to a non-empty value."
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set nRet 1
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} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
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# USE CASES:
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# 2): Current design opened AND is empty AND names same.
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# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
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# 4): Current design opened AND is empty AND names diff; design_name exists in project.
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if { $cur_design ne $design_name } {
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common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
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set design_name [get_property NAME $cur_design]
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}
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common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
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} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
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# USE CASES:
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# 5) Current design opened AND has components AND same names.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 1
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} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
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# USE CASES:
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# 6) Current opened design, has components, but diff names, design_name exists in project.
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# 7) No opened design, design_name exists in project.
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set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
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set nRet 2
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} else {
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# USE CASES:
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# 8) No opened design, design_name not in project.
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# 9) Current opened design, has components, but diff names, design_name not in project.
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common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
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create_bd_design $design_name
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common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
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current_bd_design $design_name
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}
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common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
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if { $nRet != 0 } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
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return $nRet
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}
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set bCheckIPsPassed 1
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##################################################################
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# CHECK IPs
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##################################################################
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set bCheckIPs 1
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if { $bCheckIPs == 1 } {
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set list_check_ips "\
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xilinx.com:ip:cmac_usplus:3.1\
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xilinx.com:ip:xlconstant:1.1\
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"
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set list_ips_missing ""
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common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
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foreach ip_vlnv $list_check_ips {
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set ip_obj [get_ipdefs -all $ip_vlnv]
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if { $ip_obj eq "" } {
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lappend list_ips_missing $ip_vlnv
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}
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}
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if { $list_ips_missing ne "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
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set bCheckIPsPassed 0
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}
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}
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if { $bCheckIPsPassed != 1 } {
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common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
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return 3
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}
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##################################################################
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# DESIGN PROCs
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##################################################################
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# Procedure to create entire design; Provide argument to make
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# procedure reusable. If parentCell is "", will use root.
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proc create_root_design { parentCell } {
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variable script_folder
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variable design_name
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if { $parentCell eq "" } {
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set parentCell [get_bd_cells /]
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}
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# Get object for parentCell
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set parentObj [get_bd_cells $parentCell]
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if { $parentObj == "" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
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return
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}
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# Make sure parentObj is hier blk
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set parentType [get_property TYPE $parentObj]
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if { $parentType ne "hier" } {
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catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
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return
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}
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# Save current instance; Restore later
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set oldCurInst [current_bd_instance .]
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# Set parent object as current
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current_bd_instance $parentObj
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# Create interface ports
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set core_drp [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:drp_rtl:1.0 core_drp ]
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set eth100g_rx [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_cmac_usplus:lbus_ports:2.0 eth100g_rx ]
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set eth100g_tx [ create_bd_intf_port -mode Slave -vlnv xilinx.com:display_cmac_usplus:lbus_ports:2.0 eth100g_tx ]
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set gt_serial_port_0 [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gt_rtl:1.0 gt_serial_port_0 ]
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set refclk [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 refclk ]
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set_property -dict [ list \
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CONFIG.FREQ_HZ {156250000} \
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] $refclk
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set s_axi [ create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 s_axi ]
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set_property -dict [ list \
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CONFIG.ADDR_WIDTH {32} \
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CONFIG.ARUSER_WIDTH {0} \
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CONFIG.AWUSER_WIDTH {0} \
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CONFIG.BUSER_WIDTH {0} \
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CONFIG.DATA_WIDTH {32} \
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CONFIG.HAS_BRESP {1} \
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CONFIG.HAS_BURST {0} \
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CONFIG.HAS_CACHE {0} \
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CONFIG.HAS_LOCK {0} \
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CONFIG.HAS_PROT {0} \
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CONFIG.HAS_QOS {0} \
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CONFIG.HAS_REGION {0} \
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CONFIG.HAS_RRESP {1} \
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CONFIG.HAS_WSTRB {1} \
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CONFIG.ID_WIDTH {0} \
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CONFIG.MAX_BURST_LENGTH {1} \
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CONFIG.NUM_READ_OUTSTANDING {1} \
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CONFIG.NUM_READ_THREADS {1} \
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CONFIG.NUM_WRITE_OUTSTANDING {1} \
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CONFIG.NUM_WRITE_THREADS {1} \
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CONFIG.PROTOCOL {AXI4LITE} \
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CONFIG.READ_WRITE_MODE {READ_WRITE} \
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CONFIG.RUSER_BITS_PER_BYTE {0} \
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CONFIG.RUSER_WIDTH {0} \
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CONFIG.SUPPORTS_NARROW_BURST {0} \
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CONFIG.WUSER_BITS_PER_BYTE {0} \
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CONFIG.WUSER_WIDTH {0} \
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] $s_axi
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# Create ports
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set ctl_tx_pause_req [ create_bd_port -dir I -from 8 -to 0 ctl_tx_pause_req ]
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set ctl_tx_resend_pause [ create_bd_port -dir I ctl_tx_resend_pause ]
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set drp_clk [ create_bd_port -dir I -type clk drp_clk ]
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set gt_txusrclk2 [ create_bd_port -dir O -type clk gt_txusrclk2 ]
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set_property -dict [ list \
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CONFIG.ASSOCIATED_BUSIF {eth100g_rx:eth100g_tx} \
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CONFIG.FREQ_HZ {322265625} \
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] $gt_txusrclk2
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set init_clk [ create_bd_port -dir I -type clk init_clk ]
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set pm_tick [ create_bd_port -dir I pm_tick ]
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set rx_clk [ create_bd_port -dir I -type clk -freq_hz 322265625 rx_clk ]
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set s_axi_aclk [ create_bd_port -dir I -type clk s_axi_aclk ]
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set s_axi_sreset [ create_bd_port -dir I -type rst s_axi_sreset ]
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set_property -dict [ list \
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CONFIG.POLARITY {ACTIVE_HIGH} \
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] $s_axi_sreset
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set stat_rx_aligned [ create_bd_port -dir O stat_rx_aligned ]
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set stat_rx_pause_req [ create_bd_port -dir O -from 8 -to 0 stat_rx_pause_req ]
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set sys_reset [ create_bd_port -dir I -type rst sys_reset ]
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set_property -dict [ list \
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CONFIG.POLARITY {ACTIVE_HIGH} \
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] $sys_reset
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set tx_ovfout [ create_bd_port -dir O tx_ovfout ]
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set tx_unfout [ create_bd_port -dir O tx_unfout ]
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set usr_rx_reset [ create_bd_port -dir O -type rst usr_rx_reset ]
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set usr_tx_reset [ create_bd_port -dir O -type rst usr_tx_reset ]
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# Create instance: cmac_usplus_0, and set properties
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set cmac_usplus_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cmac_usplus:3.1 cmac_usplus_0 ]
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set_property -dict [ list \
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CONFIG.CMAC_CAUI4_MODE {1} \
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CONFIG.CMAC_CORE_SELECT {CMACE4_X0Y0} \
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CONFIG.ENABLE_AXI_INTERFACE {1} \
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CONFIG.GT_DRP_CLK {100} \
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CONFIG.GT_GROUP_SELECT {X0Y4~X0Y7} \
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CONFIG.GT_REF_CLK_FREQ {156.25} \
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CONFIG.INCLUDE_AUTO_NEG_LT_LOGIC {0} \
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CONFIG.INCLUDE_RS_FEC {1} \
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CONFIG.INCLUDE_SHARED_LOGIC {2} \
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CONFIG.INCLUDE_STATISTICS_COUNTERS {1} \
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CONFIG.LANE10_GT_LOC {NA} \
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CONFIG.LANE1_GT_LOC {X0Y4} \
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CONFIG.LANE2_GT_LOC {X0Y5} \
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CONFIG.LANE3_GT_LOC {X0Y6} \
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CONFIG.LANE4_GT_LOC {X0Y7} \
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CONFIG.LANE5_GT_LOC {NA} \
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CONFIG.LANE6_GT_LOC {NA} \
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CONFIG.LANE7_GT_LOC {NA} \
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CONFIG.LANE8_GT_LOC {NA} \
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CONFIG.LANE9_GT_LOC {NA} \
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CONFIG.NUM_LANES {4x25} \
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CONFIG.RX_CHECK_ACK {0} \
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CONFIG.RX_EQ_MODE {AUTO} \
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CONFIG.RX_FLOW_CONTROL {1} \
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CONFIG.TX_FLOW_CONTROL {1} \
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CONFIG.USER_INTERFACE {LBUS} \
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] $cmac_usplus_0
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# Create instance: tie_loopback, and set properties
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set tie_loopback [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 tie_loopback ]
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set_property -dict [ list \
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CONFIG.CONST_VAL {0} \
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CONFIG.CONST_WIDTH {12} \
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] $tie_loopback
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# Create instance: tie_zero, and set properties
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set tie_zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 tie_zero ]
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set_property -dict [ list \
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CONFIG.CONST_VAL {0} \
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] $tie_zero
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# Create interface connections
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connect_bd_intf_net -intf_net RefClk_1 [get_bd_intf_ports refclk] [get_bd_intf_pins cmac_usplus_0/gt_ref_clk]
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connect_bd_intf_net -intf_net cmac_usplus_0_gt_serial_port [get_bd_intf_ports gt_serial_port_0] [get_bd_intf_pins cmac_usplus_0/gt_serial_port]
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connect_bd_intf_net -intf_net cmac_usplus_0_lbus_rx [get_bd_intf_ports eth100g_rx] [get_bd_intf_pins cmac_usplus_0/lbus_rx]
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connect_bd_intf_net -intf_net eth_100g_tx_1 [get_bd_intf_ports eth100g_tx] [get_bd_intf_pins cmac_usplus_0/lbus_tx]
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connect_bd_intf_net -intf_net sDrp_1 [get_bd_intf_ports core_drp] [get_bd_intf_pins cmac_usplus_0/core_drp]
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connect_bd_intf_net -intf_net s_axi_1 [get_bd_intf_ports s_axi] [get_bd_intf_pins cmac_usplus_0/s_axi]
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# Create port connections
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connect_bd_net -net SysClk_1 [get_bd_ports init_clk] [get_bd_pins cmac_usplus_0/init_clk]
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connect_bd_net -net aResetIn_1 [get_bd_ports sys_reset] [get_bd_pins cmac_usplus_0/sys_reset]
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connect_bd_net -net cmac_usplus_0_gt_txusrclk2 [get_bd_ports gt_txusrclk2] [get_bd_pins cmac_usplus_0/gt_txusrclk2]
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connect_bd_net -net cmac_usplus_0_stat_rx_aligned [get_bd_ports stat_rx_aligned] [get_bd_pins cmac_usplus_0/stat_rx_aligned]
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connect_bd_net -net cmac_usplus_0_stat_rx_pause_req [get_bd_ports stat_rx_pause_req] [get_bd_pins cmac_usplus_0/stat_rx_pause_req]
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connect_bd_net -net cmac_usplus_0_tx_ovfout [get_bd_ports tx_ovfout] [get_bd_pins cmac_usplus_0/tx_ovfout]
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connect_bd_net -net cmac_usplus_0_tx_unfout [get_bd_ports tx_unfout] [get_bd_pins cmac_usplus_0/tx_unfout]
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connect_bd_net -net cmac_usplus_0_usr_rx_reset [get_bd_ports usr_rx_reset] [get_bd_pins cmac_usplus_0/usr_rx_reset]
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connect_bd_net -net cmac_usplus_0_usr_tx_reset [get_bd_ports usr_tx_reset] [get_bd_pins cmac_usplus_0/usr_tx_reset]
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connect_bd_net -net ctl_tx_pause_req_1 [get_bd_ports ctl_tx_pause_req] [get_bd_pins cmac_usplus_0/ctl_tx_pause_req]
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connect_bd_net -net ctl_tx_resend_pause_1 [get_bd_ports ctl_tx_resend_pause] [get_bd_pins cmac_usplus_0/ctl_tx_resend_pause]
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connect_bd_net -net drp_clk_1 [get_bd_ports drp_clk] [get_bd_pins cmac_usplus_0/drp_clk]
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connect_bd_net -net pm_tick_1 [get_bd_ports pm_tick] [get_bd_pins cmac_usplus_0/pm_tick]
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connect_bd_net -net rx_clk_1 [get_bd_ports rx_clk] [get_bd_pins cmac_usplus_0/rx_clk]
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connect_bd_net -net s_axi_aclk_1 [get_bd_ports s_axi_aclk] [get_bd_pins cmac_usplus_0/s_axi_aclk]
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connect_bd_net -net s_axi_sreset_1 [get_bd_ports s_axi_sreset] [get_bd_pins cmac_usplus_0/s_axi_sreset]
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connect_bd_net -net tie_loopback_dout [get_bd_pins cmac_usplus_0/gt_loopback_in] [get_bd_pins tie_loopback/dout]
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connect_bd_net -net tie_zero_dout [get_bd_pins cmac_usplus_0/gtwiz_reset_rx_datapath] [get_bd_pins cmac_usplus_0/gtwiz_reset_tx_datapath] [get_bd_pins tie_zero/dout]
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# Create address segments
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assign_bd_address -offset 0x00000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces s_axi] [get_bd_addr_segs cmac_usplus_0/s_axi/Reg] -force
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# Restore current instance
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current_bd_instance $oldCurInst
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validate_bd_design
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save_bd_design
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}
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# End of create_root_design()
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##################################################################
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# MAIN FLOW
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##################################################################
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create_root_design ""
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