438 lines
20 KiB
Tcl
438 lines
20 KiB
Tcl
#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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#
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# Common timing constraints for the X4xx's motherboard CPLD.
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#
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set_time_format -unit ns -decimal_places 3
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#####################################################################
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# General
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#####################################################################
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# For a couple of 3.3V interfaces the buffer SN74AVC4T774RSVR is used to
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# increase the drive strength. For reuse we define the timings constants here.
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# For direction A to B and B to A the maximum timing varies by 0.1 ns. Taking
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# the maximum of both.
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set buffer_prop_min 0.100
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set buffer_prop_max 2.400
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#####################################################################
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# Main Clocks
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#####################################################################
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## Input clocks.
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# Reliable clock: 100.0 MHz
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set CLK_100_period 10.000
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create_clock -name CLK_100 -period $CLK_100_period [get_ports CLK_100]
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# internal PLL derived clock
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derive_pll_clocks
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# provide name for derived clocks
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set CLK_250 [get_clocks {*clk[1]}]
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# PLL output pins of the generated 50 MHz clock for internal processing
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set clk50_period 20.000
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set pll_clk_out_pin [get_pins {pll_inst|altpll_component|auto_generated|pll1|clk[0]}]
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set clk250_period 4.000
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# PLL reference clock: 64 MHz (maximum)
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set prc_clock_period 15.625
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create_clock -name PLL_REF_CLK -period $prc_clock_period [get_ports PLL_REF_CLK]
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#####################################################################
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# Timing exceptions
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#####################################################################
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## SPI slaves
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# Delay path for all synchronizers is based on the period of the
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# faster clock domain (50 MHz derived by the PLL from 100 MHz reliable clock).
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set clk50_period [expr {$CLK_100_period * 2}]
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set_max_delay -to [get_registers *synchronizer_false_path\|value\[0\]\[*\]] \
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$clk50_period
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# sclk data to CLK_100
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set_max_delay -from [get_registers *spi_slave_async\|received_word\[*\]] \
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-to [get_registers *spi_slave_async\|data_out\[*\]] \
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$clk50_period
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# PLL driven data to sclk
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set_max_delay -from [get_clocks {pll_inst*}] \
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-to [get_registers *spi_slave_async\|transmit_bits\[*\]] \
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$clk50_period
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#####################################################################
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# Power supply clocks, LEDs, DIO direction
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#####################################################################
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# Change all output signals in this section within one clock period of the
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# driving clocks.
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# Power supply clocks
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set power_supply_clocks_outputs [get_ports {PWR_SUPPLY_CLK_*}]
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set_min_delay -to $power_supply_clocks_outputs 0
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set_max_delay -to $power_supply_clocks_outputs $CLK_100_period
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# LED signals in db specific sdc
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# DIO direction
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set dio_outputs [get_ports {DIO_DIRECTION_A[*] DIO_DIRECTION_B[*]}]
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set_min_delay -to $dio_outputs 0
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set_max_delay -to $dio_outputs $clk50_period
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# Power control
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set pwr_ctrl_outputs [get_ports {IPASS_POWER_DISABLE PWR_EN_5V_OSC_100 PWR_EN_5V_OSC_122_88}]
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set_min_delay -to $pwr_ctrl_outputs 0
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set_max_delay -to $pwr_ctrl_outputs $clk50_period
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# Power fault inputs
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# Virtual clocks for constraining inputs. Using an odd clock period to
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# make sure any uncovered paths will result in timing errors due to short setup
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# or hold path.
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set power_fault_inputs [get_ports {IPASS_POWER_EN_FAULT[*]}]
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create_clock -name virtual_async_in_clk -period 4.567
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set_input_delay -clock virtual_async_in_clk 0 $power_fault_inputs
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#####################################################################
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# FPGA <-> MB CPLD PL SPI interface
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#####################################################################
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# Create clock for the PL's SPI interface.
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# PRC at least divided by 2 by the SPI Master on FPGA
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set pl_sclk_period [expr {2 * $prc_clock_period}]
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create_clock -name pl_sclk -period $pl_sclk_period [get_registers mb_cpld_sclk]
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# The SPI PL master (on the FPGA) is designed as a system synchronous
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# interface using PLL_REF_CLK.
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# The FPGA output constraints are required to calculate the windows
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# at CPLD of valid data
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# They are derived iteratively from the FPGA design ensuring a large
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# valid data period.
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set pl_spi_fpga_min_out 0.000
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set pl_spi_fpga_max_out 11.000
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# The longest trace on the PL SPI interface is (sssuming 170.0 ps/in)
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# Longest trace | Trace length | Trace delay
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# CS_0 | 7.143 in | 1.215 ns
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set pl_spi_board_delay 1.215
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# This path also contains a level translator which has a typical
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# switching time of 2.7 ns. Let's add a margin of 1 ns as worst
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# case estimation
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set pl_level_trans_delay 3.700
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# CPLD and FPGA both use PLL reference clock from a common clock chip.
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# The traces from that clock chip to the ICs are not length matched
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# Assume a worst case clock difference of 0.5 ns at the IC inputs.
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# There is no direction defined. The clock can arrive faster or slower
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# on one IC.
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set pl_clock_diff 0.500
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set pl_slave_inputs [get_ports {PL_CPLD_SCLK PL_CPLD_MOSI PL_CPLD_CS_N[*]}]
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# calculate output delays back from capturing edge, add board delay, level translator and clock difference
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set_input_delay -clock PLL_REF_CLK \
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-max [expr {$prc_clock_period - $pl_spi_fpga_max_out + $pl_spi_board_delay + $pl_level_trans_delay + $pl_clock_diff}] \
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$pl_slave_inputs
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# Assuming data is going without any delay, clock is arriving early at CPLD.
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# Negate minimum output delay as it is defined from the change to the start clock edge.
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set_input_delay -clock PLL_REF_CLK \
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-min [expr {- $pl_spi_fpga_min_out - $pl_clock_diff}] \
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$pl_slave_inputs
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# ensure large data valid window for the FPGA
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# those values are used in the FPGA / DB CPLDs
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# to calculate the input delay
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# those values are maximum integer values to still meet timing
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set pl_spi_cpld_min_out -1.000
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set pl_spi_cpld_max_out 8.000
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set pl_slave_outputs [get_ports {PL_CPLD_MISO}]
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set_output_delay -clock PLL_REF_CLK -max $pl_spi_cpld_max_out $pl_slave_outputs
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set_output_delay -clock PLL_REF_CLK -min $pl_spi_cpld_min_out $pl_slave_outputs
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#####################################################################
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# FPGA <-> MB CPLD PS SPI interface
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#####################################################################
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# Assume the PS SPI clock is maximum 5 MHz.
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# It is driven from another source and provided with the data.
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set ps_sclk_period 200.000
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create_clock -name ps_sclk -period $ps_sclk_period [get_ports PS_CPLD_SCLK]
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# The SPI PS master (on the FPGA) is wired through the MIO (Multiplexed I/O)
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# pins, meaning that the timing characteristics of the interface come from
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# the controller itself (i.e. no timed routing through PL).
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# Based on the SPI master controller specification (DS925: Table 48),
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# one may define the min/max input/output delay constraints.
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set ps_spi_tco_min -2.000
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set ps_spi_tco_max 5.000
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set ps_spi_miso_setup -2.000
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set ps_spi_miso_hold [expr {0.3 * $ps_sclk_period}]
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# Use the worst-case board propagation delays.
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# Assuming 170.0 ps/in.
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# Longest trace | Trace length | Trace delay
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# CS0_n | 4.735 in | 0.805 ns
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# --------------------------------------------
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set ps_spi_board_delay 0.805
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set ps_slave_inputs [get_ports {PS_CPLD_MOSI PS_CPLD_CS_N[*]}]
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# clock is immediately available, data is taking maximum time
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# SPI data in CPOL=CPHA=1 is driven on the falling sclk edge
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set ps_sclk_max_in_delay [expr {$ps_spi_tco_max + $ps_spi_board_delay}]
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set_input_delay -clock ps_sclk -clock_fall \
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-max $ps_sclk_max_in_delay \
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$ps_slave_inputs
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# fast data and clock delayed (reducing data delay)
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set_input_delay -clock ps_sclk -clock_fall \
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-min [expr {$ps_spi_tco_min - $ps_spi_board_delay}] \
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$ps_slave_inputs
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set ps_slave_outputs [get_ports {PS_CPLD_MISO}]
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# use only half the frequency because falling edge is driving data
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set_output_delay -clock ps_sclk \
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-max [expr {$ps_spi_miso_setup + 2*$ps_spi_board_delay}] \
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$ps_slave_outputs
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# use hold requirement only as clock and data propagation further
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# delay the signal
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set_output_delay -clock ps_sclk \
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-min [expr {-$ps_spi_miso_hold}] \
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$ps_slave_outputs
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# Chip select signals are captured for binary decoding in 250 MHz clock domain.
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# To be able to specify a maximum delay for the data path only a second set of
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# input delays is added to the root clock of the 250 MHz domain.
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set_input_delay -add_delay -clock CLK_100 0 [get_ports {PS_CPLD_CS_N[*]}]
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# Declare paths between the 2 clock domains as false paths
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set_false_path -from [get_clocks {CLK_100}] -to [get_ports {PS_CPLD_MISO}]
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set_false_path -from [get_clocks {ps_sclk}] -to [get_registers {synchronizer:ps_spi_input_sync_inst*}]
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# Specify maximum data path delay
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set_max_delay -from [get_ports {PS_CPLD_CS_N[*]}] -to $CLK_250 $clk250_period
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#####################################################################
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# MB CPLD PS SPI passthrough common
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#####################################################################
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###### Binary CS decoding ######
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# The CS outputs for the external SPI slaves are driven from a 250 MHz clock to
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# ensure glitch free switching after binary encoding. Additionally those signals
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# have to meet the setup and hold requirements of the SPI slaves operating at
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# ps_sclk (5 MHz). CS lines typically are asserted half a clock period of sclk
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# before any active edge of sclk. The constraints below are using multi-cycle
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# paths to provide the placer with information about the clock multiplier from
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# ps_sclk to 250 MHz. Furthermore they incorporate the time required for
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# decoding by lowering the clock multiplier as shown in the waveform below
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# (multiplier is not shown correctly).
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#
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# ps_sclk -\__________________________________________________/--------
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# 250 MHz _/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\_/-\-
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# CS @ CPLD input X>--------------- stable ------------------------------------
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# CS @ CPLD output ---------<XXXXXXX>-------------- stable ---------------------
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# |<----->| min decoding delay
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# |<----->| change window
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# --------------->| SPI slave hold requirement
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# SPI slave setup requirement |<-------------------------------->|
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#
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# Get port to apply the multi-cycle constraint.
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set binary_cs_ports [get_ports {LMK32_CS_N TPM_CS_N PHASE_DAC_CS_N CLK_DB_CS_N}]
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# Determine number of full 250 MHz periods within half a period of ps_sclk.
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set ps_spi_clock_divider [expr {int($ps_sclk_period/$clk250_period/2)}]
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# Setup multi-cycle accounts for
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# - one clock cycle data path delay from port to first register stage
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# - one clock cycle to resolve meta-stability
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# - up to 3 register stages internally (port to ps_cpld_cs_n_shift3)
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# - one output register stage (registers on each $binary_cs_ports)
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# Static timing analysis will take the data path from register to output port
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# into account.
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# The number of 250 MHz periods is reduced by a total of 7 clock cycles (listed
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# above) to match the SPI slave setup requirement time shown in the waveform
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# above. The slave's setup time in ps_sclk domain is specified below for each
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# individual slave.
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set ps_spi_setup_multicycle [expr {$ps_spi_clock_divider - 7}]
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set_multicycle_path -setup -start -to $binary_cs_ports $ps_spi_setup_multicycle
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# Hold multicycle accounts for
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# - min 2 synchronization register stages internally (ps_cpld_cs_n_shift2)
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# (= min one clock cycle delay as data could arrive just before setup
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# requirement of first register stages assuming no data delay)
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# - one output register stage
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# Static timing analysis will take the data path from register to output port
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# into account.
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# As the clock edge for hold analysis is shifted with the setup edge the number
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# of multi cycles has to be increased by this amount of cycles to get back to
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# the falling edge of ps_sclk. Furthermore CS lines are released one half
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# ps_sclk period after the last data transfer. So hold delay is increased by an
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# additional half clock cycle.
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set ps_spi_hold_multicycle [expr {$ps_spi_clock_divider + $ps_spi_setup_multicycle - 2}]
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set_multicycle_path -hold -start -to $binary_cs_ports $ps_spi_hold_multicycle
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###### local SPI slave ######
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# The chip select path for the MB CPLD itself is driven in the 250 MHz clock
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# domain and captured by registers operating at ps_sclk. Therefore setting the
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# path as false path preventing the placer from adding additional routing delay
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# to ensure hold timing. The setup path is limited to a maximum extend of one
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# clock period. As this path crosses clock domains clock propagation is included
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# in this path during static timing analysis. The TCL analysis in
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# scripts/ps_cs_analysis.tcl ensures a maximum value for data excluding the
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# clocking network.
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set_false_path -from [get_registers {ps_spi_cs_n_decoded[0]}] -hold
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set_max_delay -from [get_registers {ps_spi_cs_n_decoded[0]}] $clk250_period
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###### LMK04832 ######
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create_generated_clock -source [get_ports PS_CPLD_SCLK] \
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-name lmk_spi_sclk [get_ports LMK32_SCLK]
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# Use the worst-case board propagation delays.
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# Assuming 170.0 ps/in.
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# Longest trace | Trace length | Trace delay
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# LMK32_SCLK | 8.259 in | 1.404 ns
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# --------------------------------------------
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set lmk_board_delay 1.404
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# setup and hold dominated by CS <-> SCK relationship
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set lmk_setup 20.000
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set lmk_hold 20.000
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set lmk_tco_max 60.000
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set lmk_outputs [get_ports {LMK32_MOSI LMK32_CS_N}]
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set_output_delay -clock lmk_spi_sclk \
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-max [expr {$lmk_setup + $lmk_board_delay + $buffer_prop_max}] \
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$lmk_outputs
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set_output_delay -clock lmk_spi_sclk \
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-min [expr {-$lmk_hold - $lmk_board_delay - $buffer_prop_min}] \
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$lmk_outputs
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set lmk_inputs [get_ports {LMK32_MISO}]
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set_input_delay -clock lmk_spi_sclk -clock_fall \
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-max [expr {$lmk_tco_max + 2*$lmk_board_delay + 2*$buffer_prop_max}] \
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$lmk_inputs
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set_input_delay -clock lmk_spi_sclk -clock_fall \
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-min [expr {2*$buffer_prop_min}] \
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$lmk_inputs
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###### Phase DAC ######
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create_generated_clock -source [get_ports PS_CPLD_SCLK] \
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-name phase_dac_spi_sclk [get_ports PHASE_DAC_SCLK]
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# Use the worst-case board propagation delays.
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# Assuming 170.0 ps/in.
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# Longest trace | Trace length | Trace delay
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# SpiDCs3v3_n | 8.322 in | 1.415 ns
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# --------------------------------------------
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set phase_dac_board_delay 1.415
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#setup dominated by SYNC signal
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set phase_dac_setup 13.000
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set phase_dac_hold 5.000
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# device captures data on falling clock edge (CPOL = 1)
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# constraining it as it would be like all the other SPI modules
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# PS SPI master is responsible for changing SPI mode when talking
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# to this device
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set phase_dac_outputs [get_ports {PHASE_DAC_MOSI PHASE_DAC_CS_N}]
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set_output_delay -clock phase_dac_spi_sclk -clock_fall \
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-max [expr {$phase_dac_setup + $phase_dac_board_delay}] \
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$phase_dac_outputs
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set_output_delay -clock phase_dac_spi_sclk -clock_fall \
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-min [expr {-$phase_dac_hold - $phase_dac_board_delay}] \
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$phase_dac_outputs
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###### TPM ######
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create_generated_clock -source [get_ports PS_CPLD_SCLK] \
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-name tpm_spi_sclk [get_ports TPM_SCLK]
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# Use the worst-case board propagation delays.
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# Assuming 170.0 ps/in.
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# Longest trace | Trace length | Trace delay
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# TPM_CS_n | 1.128 in | 0.196 ns
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# --------------------------------------------
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set tpm_board_delay 0.196
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#tco dominated by NSS signal
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set tpm_setup 5.000
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set tpm_hold 5.000
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set tpm_tco_max 25.000
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set tpm_outputs [get_ports {TPM_MOSI TPM_CS_N}]
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set_output_delay -clock tpm_spi_sclk \
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-max [expr {$tpm_setup + $tpm_board_delay}] \
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$tpm_outputs
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set_output_delay -clock tpm_spi_sclk \
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-min [expr {-$tpm_hold - $tpm_board_delay}] \
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$tpm_outputs
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set tpm_inputs [get_ports {TPM_MISO}]
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set_input_delay -clock tpm_spi_sclk -clock_fall \
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-max [expr {$tpm_tco_max + 2*$tpm_board_delay}] \
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$tpm_inputs
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set_input_delay -clock tpm_spi_sclk -clock_fall \
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-min 0 \
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$tpm_inputs
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#### Clocking AUX board SPI interface ####
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# Rev B clocking aux board uses a LMK05318 connected to this interface
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# Using its timing for this interface.
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create_generated_clock -source [get_ports PS_CPLD_SCLK] \
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-name clk_db_clk_out [get_ports CLK_DB_SCLK]
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set clk_db_setup 10.000
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set clk_db_hold 10.000
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set clk_db_tco_max 20.000
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# Just a worst case assumption based on 2 times the MB trace length CLK_DB_MOSI.
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# The multiplier 2 accounts for any traces on the CLK AUX board.
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set clk_db_board_delay 4.000
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set clk_db_outputs [get_ports {CLK_DB_CS_N CLK_DB_MOSI}]
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# Output signals have to stable for max setup and propagation time. Clock delay
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# to device is expected to be 0 in this equation.
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set_output_delay -clock clk_db_clk_out \
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-max [expr {$clk_db_setup + $clk_db_board_delay + $buffer_prop_max}] $clk_db_outputs
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# The min output delay is comprised of:
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# - device required hold time ($clk_db_hold)
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# - max clock propagation delay ($clk_db_board_delay)
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# - min data propagation time (0)
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# All terms have to be negated as min output delay is defined in opposite
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# direction (positive into the past).
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set_output_delay -clock clk_db_clk_out \
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-min [expr {-$clk_db_hold - $clk_db_board_delay - $buffer_prop_min}] $clk_db_outputs
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set clk_db_inputs [get_ports {CLK_DB_MISO}]
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# Max delay calculated is based on
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# - max clock delay ($clk_db_board_delay)
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# - max clock to out LMK ($clk_db_tco_max)
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# - max data path delay ($clk_db_board_delay)
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set_input_delay -clock clk_db_clk_out -clock_fall \
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-max [expr {$clk_db_tco_max + $clk_db_board_delay*2 + 2*$buffer_prop_max}] $clk_db_inputs
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# Min delay assumes clock propagates to device and data propagates to CPLD
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# without any delays.
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set_input_delay -clock clk_db_clk_out -clock_fall \
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-min [expr {2*$buffer_prop_min}] $clk_db_inputs
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#####################################################################
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# PCIe signals
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#####################################################################
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# I²C bus is operated at 100kHz. Constraints would not improve timing
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# significantly (typically in the order of nanoseconds, which is negligible
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# given the SCL period of 10 us).
|
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# PCI-Express reset signal is not timing critical as it is received
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# asynchronously by the FPGA.
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set_false_path -to [get_ports {IPASS_SDA[0] IPASS_SCL[0] PCIE_RESET}]
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# I²C inputs are only consumed by synchronizers.
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# Add exceptions for all known consumers.
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|
set_false_path -to [get_registers {PcieCmiWrapper:pcie_cmi_inst|PcieCmi:PcieCmix|UsfCablePort:UsfCablePortx|CablePort:CablePortx|I2cTop:CableI2cx|I2cMonitor:I2cMonitorx|I2cFilter:I2cFilterx|I2cSigFilter:SclFilterx|fSig_ms}]
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|
set_false_path -to [get_registers {PcieCmiWrapper:pcie_cmi_inst|PcieCmi:PcieCmix|UsfCablePort:UsfCablePortx|CablePort:CablePortx|I2cTop:CableI2cx|I2cMonitor:I2cMonitorx|I2cFilter:I2cFilterx|I2cSigFilter:SdaFilterx|fSig_ms}]
|
|
set_false_path -to [get_registers {PcieCmiWrapper:pcie_cmi_inst|PcieCmi:PcieCmix|UsfCablePort:UsfCablePortx|CablePort:CablePortx|StuckBusFixer:StuckBusFixerx|DoubleSyncSlAsyncIn:DoubleSclkx|DoubleSyncAsyncInBase:DoubleSyncAsyncInBasex|DFlopAsync:oSig_msx|lpm_ff:LPM_FFx|dffs[0]}]
|
|
set_false_path -to [get_registers {PcieCmiWrapper:pcie_cmi_inst|PcieCmi:PcieCmix|UsfCablePort:UsfCablePortx|CablePort:CablePortx|StuckBusFixer:StuckBusFixerx|DoubleSyncSlAsyncIn:DoubleSdax|DoubleSyncAsyncInBase:DoubleSyncAsyncInBasex|DFlopAsync:oSig_msx|lpm_ff:LPM_FFx|dffs[0]}]
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|
|
|
#####################################################################
|
|
# Known Issue of On-Chip Flash
|
|
#####################################################################
|
|
# see https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/tools/2016/warning--332060---node---alteraonchipflash-onchipflash-alteraonc.html
|
|
create_generated_clock -name flash_se_neg_reg \
|
|
-source [get_pins { on_chip_flash:flash_inst|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|clk }] \
|
|
-divide_by 2 [get_pins { on_chip_flash:flash_inst|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_se_neg_reg|q } ]
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|
|
|
#####################################################################
|
|
# Clock uncertainty
|
|
#####################################################################
|
|
# Assign some uncertainty to all clocks
|
|
set clock_uncertainty 0.150
|
|
set_clock_uncertainty -to [get_clocks *] $clock_uncertainty
|
|
derive_clock_uncertainty
|