24 lines
961 B
Tcl
24 lines
961 B
Tcl
#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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# Clock definition constraints for X440
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#
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###############################################################################
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# MMCM-Related Clocks
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#
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# Note: Vivado will create generated clocks based on the default MMCM settings
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# configured in the clocking wizard, but we are going to dynamically change
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# those clocks, and so the MMCM has to be configured for the highest frequency.
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###############################################################################
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# PLL Reference Clock (PRC) input. This goes from the LMK straight to the MMCM
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# input, and is used to generate the internal PRC as well as RFDC/data clocks.
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# Set to maximum frequency of 64 MHz. Actual frequency depends on the LMK
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# configuration.
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set pll_ref_clk_period 15.625
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create_clock -name pll_ref_clk -period $pll_ref_clk_period [get_ports PLL_REFCLK_FPGA_P]
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