miegl/b210-k7-fpga
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b210-k7-fpga/sim/rfnoc
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Wade Fife bfef20ea45 fpga: sim: Add slave_idle() to PkgAxiStreamBfm.sv 
Original-commit: f706b89e6974e28ce76aadeeb06169becc86acba
2021-06-10 11:56:58 -05:00
..
test/ChdrIfaceBfm
sim: Add ChdrIfaceBfm test
2020-03-09 13:43:05 -05:00
Makefile.srcs
fpga: lib: Add synthesizable AXI4-Stream SV components
2020-06-25 14:44:04 -05:00
PkgAxiLiteBfm.sv
fpga: sim: Fix AxiLiteBfm
2020-07-31 13:10:00 -05:00
PkgAxisCtrlBfm.sv
fpga: lib: Add synthesizable AXI4-Stream SV components
2020-06-25 14:44:04 -05:00
PkgAxiStreamBfm.sv
fpga: sim: Add slave_idle() to PkgAxiStreamBfm.sv
2021-06-10 11:56:58 -05:00
PkgChdrBfm.sv
fpga: sim: Fix stream command and status models
2020-08-31 08:16:43 -05:00
PkgChdrData.sv
fpga: sim: Add packet_info_equal function
2020-05-28 15:04:05 -05:00
PkgChdrIfaceBfm.sv
fpga: sim: Add packet_info_equal function
2020-05-28 15:04:05 -05:00
PkgChdrUtils.sv
sim: Parameterize chdr_word_t data type
2020-03-09 13:43:05 -05:00
PkgCtrlIfaceBfm.sv
sim: Split PkgRfnocBlockCtrlBfm into separate packages
2020-03-09 13:43:05 -05:00
PkgEthernet.sv
fpga: sim: Update PkgEthernet
2020-07-31 13:22:29 -05:00
PkgRfnocBlockCtrlBfm.sv
fpga: sim: Add packet_info_equal function
2020-05-28 15:04:05 -05:00
PkgRfnocItemUtils.sv
fpga: rfnoc: Add support for 512-bit CHDR widths
2020-06-18 09:09:34 -05:00
PkgTestExec.sv
fpga: rfnoc: Add support for 512-bit CHDR widths
2020-06-18 09:09:34 -05:00
sim_clock_gen.sv
fpga: lib: Add PHASE parameter to sim_clk_gen
2021-06-03 11:26:54 -05:00
sim_rfnoc_lib.svh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
test_exec.svh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00