Wade Fife
dce6ce8063
This updates the makefiles for the testbenches so they can be run using "make modelsim" without any additional hacks. The "xsim" and "vsim" simulation targets also still work. Original-commit: e962cc4a5e51e2326eb656ee2a779ea26774687b
47 lines
1.4 KiB
Makefile
47 lines
1.4 KiB
Makefile
#
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# Copyright 2018 Ettus Research, A National Instruments Company
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../../top)
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Include makefiles and sources for the DUT and its dependencies
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include $(BASE_DIR)/../lib/dsp/Makefile.srcs
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DESIGN_SRCS = $(abspath \
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$(DSP_SRCS) \
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)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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# Define toplevel module
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SIM_TOP = mult_add_clip_tb glbl
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# Add test bench, user design under test, and
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# additional user created files
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SIM_SRCS = $(abspath \
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mult_add_clip_tb.sv \
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$(VIVADO_PATH)/data/verilog/src/glbl.v \
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)
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# MODELSIM_USER_DO = $(abspath wave.do)
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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