Ashish Chaudhari
adf2da6ac7
- Fixed 10GigE firmware communication issues and sequence errors for TX - Multiple changes to help ease timing closure - Cleaned up build scripts - Switched to Xilinx ISE 14.7 as the default build tool for X300 Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0
8 lines
289 B
Plaintext
8 lines
289 B
Plaintext
NET XG_CLK_p IOSTANDARD = LVDS_25 | LOC = R8;
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NET "XG_CLK_p" TNM_NET = XG_CLK_p;
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TIMESPEC TS_XG_CLK_p = PERIOD "XG_CLK_p" 6400 ps HIGH 50%;
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NET XG_CLK_n IOSTANDARD = LVDS_25 | LOC = R7;
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NET "XG_CLK_n" TNM_NET = XG_CLK_n;
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TIMESPEC TS_XG_CLK_n = PERIOD "XG_CLK_n" TS_XG_CLK_p HIGH 50%;
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