61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
109 lines
2.9 KiB
Verilog
109 lines
2.9 KiB
Verilog
//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: db_gpio_reordering
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//
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// Description:
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// Reorders the GPIO wires towards the DB CPLDs in a common way for DB 0 and 1.
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//
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// The digital daughterboard connector has 120 pins [A-F][1-20].
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// The numbering on the motherboard traces do not match for daughterboard 0 and 1.
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// This module orders the FPGA outputs MSB first and connects it to the DB
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// connection with increasing letter and increasing number.
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// For DB 0 this results in:
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// FPGA Bit 19 = A7 (trace: DB0/1_GPIO[19])
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// FPGA Bit 18 = A8 (trace: DB0/1_GPIO[17])
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// ...
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// FPGA Bit 0 = C19 (trace: DB0/1_GPIO[12])
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// This enables usages of the same daughterboard CPLD image on both connectors.
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//
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`default_nettype none
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module db_gpio_reordering (
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// 20 bit internal interface
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output wire [19:0] db0_gpio_in_int,
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input wire [19:0] db0_gpio_out_int,
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input wire [19:0] db0_gpio_out_en_int,
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output wire [19:0] db1_gpio_in_int,
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input wire [19:0] db1_gpio_out_int,
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input wire [19:0] db1_gpio_out_en_int,
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// 20 bit external interface
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input wire [19:0] db0_gpio_in_ext,
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output wire [19:0] db0_gpio_out_ext,
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output wire [19:0] db0_gpio_out_en_ext,
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input wire [19:0] db1_gpio_in_ext,
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output wire [19:0] db1_gpio_out_ext,
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output wire [19:0] db1_gpio_out_en_ext
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);
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//port indexes
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localparam ENTRY_BITWIDTH = 5;
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localparam NUM_ENTRIES = 20;
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localparam [ENTRY_BITWIDTH*NUM_ENTRIES-1:0] PORT0_MAPPING = {
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5'd 19,
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5'd 17,
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5'd 0,
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5'd 14,
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5'd 15,
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5'd 10,
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5'd 4,
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5'd 5,
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5'd 16,
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5'd 18,
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5'd 8,
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5'd 6,
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5'd 1,
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5'd 9,
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5'd 2,
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5'd 3,
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5'd 11,
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5'd 7,
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5'd 13,
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5'd 12 };
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localparam [ENTRY_BITWIDTH*NUM_ENTRIES-1:0] PORT1_MAPPING = {
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5'd 10,
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5'd 6,
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5'd 7,
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5'd 2,
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5'd 3,
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5'd 0,
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5'd 1,
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5'd 4,
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5'd 8,
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5'd 9,
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5'd 11,
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5'd 5,
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5'd 13,
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5'd 12,
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5'd 15,
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5'd 14,
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5'd 19,
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5'd 18,
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5'd 17,
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5'd 16 };
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// reordering assignments
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generate
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genvar i;
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for (i=0; i<NUM_ENTRIES; i=i+1) begin : reordering_gen
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// input data
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assign db0_gpio_in_int[i] = db0_gpio_in_ext[PORT0_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]];
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assign db1_gpio_in_int[i] = db1_gpio_in_ext[PORT1_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]];
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// output data
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assign db0_gpio_out_ext[PORT0_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]] = db0_gpio_out_int[i];
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assign db1_gpio_out_ext[PORT1_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]] = db1_gpio_out_int[i];
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// output enable
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assign db0_gpio_out_en_ext[PORT0_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]] = db0_gpio_out_en_int[i];
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assign db1_gpio_out_en_ext[PORT1_MAPPING[i*ENTRY_BITWIDTH +: ENTRY_BITWIDTH]] = db1_gpio_out_en_int[i];
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end
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endgenerate
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endmodule
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`default_nettype wire
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