372 lines
12 KiB
Systemverilog
372 lines
12 KiB
Systemverilog
//
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// Copyright 2023 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: align_samples_tb
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//
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// Description:
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//
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// Testbench for axis_pkt_throttle.
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//
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`default_nettype none
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module axis_pkt_throttle_tb ();
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// Include macros and time declarations for use with PkgTestExec
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`include "test_exec.svh"
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import PkgTestExec::*;
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import PkgRandom::*;
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localparam real CLK_PERIOD = 10.0;
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localparam int THROTTLE_W = 8;
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localparam int DATA_W = 32;
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localparam int MTU = 4;
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localparam int MAX_PKT_LEN = 2**MTU;
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localparam int NUM_PACKETS = 100;
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localparam int FRAC_W = THROTTLE_W/2;
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localparam int WHOLE_W = THROTTLE_W - FRAC_W;
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//---------------------------------------------------------------------------
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// Clocks and Resets
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//---------------------------------------------------------------------------
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bit clk;
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bit rst;
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sim_clock_gen #(.PERIOD(CLK_PERIOD))
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clk_gen (.clk(clk), .rst(rst));
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//---------------------------------------------------------------------------
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// Device Under Test (DUT)
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//---------------------------------------------------------------------------
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logic [THROTTLE_W-1:0] throttle;
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logic [DATA_W-1:0] i_tdata;
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logic i_tlast;
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logic i_tvalid;
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logic i_tready;
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logic [DATA_W-1:0] o_tdata;
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logic o_tlast;
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logic o_tvalid;
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logic o_tready;
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axis_pkt_throttle #(
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.THROTTLE_W(THROTTLE_W),
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.DATA_W (DATA_W),
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.MTU (MTU)
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) axis_pkt_throttle_dut (
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.clk (clk ),
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.rst (rst ),
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.throttle(throttle),
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.i_tdata (i_tdata ),
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.i_tlast (i_tlast ),
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.i_tvalid(i_tvalid),
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.i_tready(i_tready),
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.o_tdata (o_tdata ),
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.o_tlast (o_tlast ),
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.o_tvalid(o_tvalid),
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.o_tready(o_tready)
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);
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//---------------------------------------------------------------------------
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// Tests
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//---------------------------------------------------------------------------
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// Run a test using the following parameters.
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//
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// num_pkts : Number of packets to generate, each with a random
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// length.
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// input_stall_prob : Probability of a stall on the input, a whole number
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// from 0 to 99.
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// output_stall_prob : Probability of a stall on the output, a whole number
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// from 0 to 99.
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// rate : Floating point value in the range (0, 1.0].
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// min_pkt_length : Minimum packet length to generate.
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//
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task automatic run_test(
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int num_pkts,
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real rate = 1.0,
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int input_stall_prob = 0,
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int output_stall_prob = 0,
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int min_pkt_length = 1
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);
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real actual_rate;
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test.start_test(
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$sformatf({ "num_pkts=%0d, rate=%0.3f, input_stall_prob=%0d, ",
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"output_stall_prob=%0d, min_pkt_length=%0d"},
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num_pkts, rate, input_stall_prob, output_stall_prob)
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);
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throttle = (1.0/rate-1.0) * 2.0**FRAC_W;
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actual_rate = 1.0/(real'(throttle)/(2.0**FRAC_W) + 1.0);
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$display("Setting throttle to 0x%X (rate = %0.3f)", throttle, actual_rate);
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i_tdata <= 'X;
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i_tlast <= 'X;
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i_tvalid <= 0;
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o_tready <= 0;
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@(posedge clk);
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fork
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// The writer generates random packets to input to the DUT
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begin : writer
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logic [DATA_W-1:0] data = 0;
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for (int pkt_count = 0; pkt_count < num_pkts; pkt_count++) begin
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int pkt_length = $urandom_range(min_pkt_length, MAX_PKT_LEN);
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for (int word_count = 0; word_count < pkt_length; word_count++) begin
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// Write the next word
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i_tdata <= data;
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i_tlast <= (word_count == pkt_length-1);
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i_tvalid <= 1;
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do @(posedge clk); while (!(i_tvalid && i_tready));
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data = data + 1;
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// Randomly stall between words
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if ($urandom_range(99) < input_stall_prob) begin
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i_tdata <= 'X;
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i_tlast <= 'X;
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i_tvalid <= 0;
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do @(posedge clk); while ($urandom_range(99) < input_stall_prob);
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end
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end
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end
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end : writer
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// The data_checker verifies that the data output is correct and handles
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// random stalling of the output stream.
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begin : data_checker
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logic [DATA_W-1:0] data = 0;
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for (int pkt_count = 0; pkt_count < num_pkts; pkt_count++) begin
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int word_count = 0;
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forever begin
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@(posedge clk);
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if (o_tvalid && o_tready) begin
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`ASSERT_ERROR(
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o_tdata == data,
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$sformatf({
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"Data didn't match expected on packet %0d word offset %0d. ",
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"Expected %X, read %X"},
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pkt_count, word_count, data, o_tdata
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)
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)
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data++;
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if (i_tlast) break;
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word_count++;
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end
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// Randomly stall this cycle
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o_tready <= ($urandom_range(99) >= output_stall_prob);
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end
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end
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end : data_checker
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// The throttle_checker measures the packet rate and confirms that it
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// matches the configured rate.
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begin : throttle_checker
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bit sop = 0; // Start of packet indicator
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realtime sop_time; // Time at which the packet started
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int pkt_length; // Counter to measure packet length (number of transfers)
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int pkt_duration; // Counter to measure packet duration (from start to tlast)
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// Wait for the start of the first packet
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forever begin
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@(posedge clk);
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if (o_tvalid && o_tready) begin
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sop_time = $realtime;
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sop = o_tlast;
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break;
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end
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end
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// Iterate through packets
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pkt_length = 1;
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pkt_duration = 1;
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for (int pkt_count = 0; pkt_count < num_pkts; pkt_count++) begin : pkt_loop
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int exp_pkt_cycles;
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forever begin : cycle_loop
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@(posedge clk);
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if (!sop) pkt_duration++;
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if (o_tvalid && o_tready) begin : transfer_cycle
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// Calculate the minimum allowed time between packets assuming
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// continuous data.
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exp_pkt_cycles = int'(real'(pkt_length) / actual_rate);
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// Check if this is the first transfer of a packet. If so, verify
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// that the duration of the previous packet was not shorter than
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// the configured rate would allow.
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if (sop) begin : first_transfer
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int pkt_cycles;
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// Calculate the actual time between packets.
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pkt_cycles = ($realtime - sop_time) / CLK_PERIOD;
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if (input_stall_prob == 0 && output_stall_prob == 0) begin
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// If there are no stalls, the actual time should exactly
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// match the expected, or one less due to rounding.
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`ASSERT_ERROR(
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pkt_cycles == exp_pkt_cycles || pkt_cycles == exp_pkt_cycles-1,
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$sformatf({
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"Time for packet %0d did not match expected range.\n",
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" Actual Rate: %f\n",
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" Packet Length: %0d\n",
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" Packet Cycles: %0d\n",
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" Expected Cycles: %0d"},
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pkt_count, actual_rate, pkt_length, pkt_cycles, exp_pkt_cycles
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)
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)
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end else begin
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// If there are stalls, the actual length should never be
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// less than the min expected, but could be substantially
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// more.
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`ASSERT_ERROR(
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pkt_cycles >= exp_pkt_cycles-1,
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$sformatf({
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"Time for packet %0d was less than expected.\n",
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" Actual Rate: %f\n",
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" Packet Length: %0d\n",
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" Packet Cycles: %0d\n",
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" Expected Cycles: %0d"},
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pkt_count, actual_rate, pkt_length, pkt_cycles, exp_pkt_cycles
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)
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)
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end
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// Setup measurement of the packet we just started
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sop = o_tlast;
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pkt_length = 1;
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pkt_duration = 1;
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sop_time = $realtime;
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break;
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end : first_transfer
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else begin : subsequent_transfer
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pkt_length++;
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end : subsequent_transfer
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sop = o_tlast;
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end : transfer_cycle
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else begin : idle_cycle
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// Calculate the minimum allowed time between packets assuming
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// continuous data.
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int exp_pkt_cycles = int'(real'(pkt_length) / actual_rate);
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// If the packet duration was longer than the expected packet
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// time, then we should NOT be gating packet flow.
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if (pkt_duration > exp_pkt_cycles) begin
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`ASSERT_ERROR(
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axis_pkt_throttle_dut.gate == 0,
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"The throttle gate engaged when it should not have."
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)
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end
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end
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// If we're on the last packet, then there won't be another start
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// of packet to measure against, so there's nothing left to check.
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if (sop && (pkt_count == num_pkts-1)) break;
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end : cycle_loop
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end : pkt_loop
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end : throttle_checker
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join
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test.end_test();
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endtask : run_test
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//---------------------------------------------------------------------------
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// Underflow Tracker
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//---------------------------------------------------------------------------
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int uflow_rise_count = 0;
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int uflow_fall_count = 0;
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logic uflow_prev = 0;
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always @(posedge clk) begin
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uflow_prev <= axis_pkt_throttle_dut.underflow;
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if (axis_pkt_throttle_dut.underflow && !uflow_prev) begin
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uflow_rise_count <= uflow_rise_count + 1;
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end
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if (!axis_pkt_throttle_dut.underflow && uflow_prev) begin
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uflow_fall_count <= uflow_fall_count + 1;
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end
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end
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//---------------------------------------------------------------------------
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// Main Test Process
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//---------------------------------------------------------------------------
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initial begin : tb_main
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string tb_name;
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tb_name = $sformatf("axis_pkt_throttle");
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test.start_tb(tb_name, 20ms);
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//--------------------------------
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// Reset
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//--------------------------------
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test.start_test("Reset", 1ms);
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clk_gen.reset();
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if (rst) @rst;
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test.end_test();
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//--------------------------------
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// Test Sequences
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//--------------------------------
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begin
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// List various rate settings and handshake stall behaviors to test
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automatic real rates[] = '{
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0.10,
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0.25,
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0.50,
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0.75,
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0.90,
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1.00
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};
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automatic real stall_probs[] = '{
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0,
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25,
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50,
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75
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};
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// Test each permutation of rates and stall probabilities
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foreach (rates[i]) begin
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foreach (stall_probs[j]) begin
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foreach (stall_probs[k]) begin
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run_test(NUM_PACKETS, rates[i], stall_probs[j], stall_probs[k]);
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end
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end
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end
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end
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begin
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// Test really slow packets to make sure the internal counters handle
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// underflow correctly.
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localparam int NUM_UFLOW_PACKETS = 4;
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run_test(NUM_UFLOW_PACKETS, 0.1, 99, 99, MAX_PKT_LEN/2);
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// Follow up with regular packets
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run_test(2);
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`ASSERT_ERROR(
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uflow_rise_count == uflow_fall_count && uflow_rise_count == NUM_UFLOW_PACKETS,
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"Underflow did not occur as expected."
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)
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end
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//--------------------------------
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// Finish Up
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//--------------------------------
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test.end_tb();
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end : tb_main
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endmodule : axis_pkt_throttle_tb
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`default_nettype wire
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