miegl/b210-k7-fpga
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b210-k7-fpga/top/x300
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Wade Fife 6f2cbbfd16 x300: Add protover and chdr_width regs to x300_mb_iface 
Original-commit: ec74e70cd0f44b780cef2303fc513cff3f232b10
2022-06-14 07:38:54 -05:00
..
coregen_dsp
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ip
x300: Expand DRAM address space to 1G
2020-05-18 17:50:38 -05:00
sim
fpga: Update testbenches to work in ModelSim
2021-06-17 08:16:59 -05:00
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build_x300.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
bus_int.v
x300: Add protover and chdr_width regs to x300_mb_iface
2022-06-14 07:38:54 -05:00
capture_ddrlvds.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dev_config.json
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
gen_ddrlvds.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile.x300.inc
fpga: Use PROTOVER and CHDR_W from RFNoC image builder
2022-03-29 14:45:04 -05:00
nirio_chdr64_adapter.v
fpga: remove liberio
2020-07-20 16:01:03 -05:00
setupenv.sh
fpga: Set default part for sim in setupenv.sh
2021-08-30 08:20:10 -05:00
soft_ctrl.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
timing.xdc
fpga: x300: Update synchronizer constraint
2021-09-13 13:20:37 -05:00
x3x0_base.lvbitx
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_1ge.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_10ge_port0.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_10ge_port1.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_10ge.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_aurora.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_core.v
fpga: x300: OR ATR signals going into db_control
2021-12-07 12:11:35 -06:00
x300_dram.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_eth_interface.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_pcie_int.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300_rfnoc_image_core.v
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
x300_rfnoc_image_core.vh
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
x300_rfnoc_image_core.yml
fpga: rfnoc: Remove rfnoc_version from target YAML
2022-05-11 12:29:35 -07:00
x300_sfpp_io_core.v
x300: Fix sfpp_io_core tuser width
2021-08-27 08:24:07 -05:00
x300_static_router.hex
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
x300_zpu_config.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x300.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
x310_rfnoc_image_core.v
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
x310_rfnoc_image_core.vh
fpga: Update all RFNoC images
2022-03-31 13:51:23 -07:00
x310_rfnoc_image_core.yml
fpga: rfnoc: Remove rfnoc_version from target YAML
2022-05-11 12:29:35 -07:00
x310_static_router.hex
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00