60 lines
1.2 KiB
Verilog
60 lines
1.2 KiB
Verilog
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task serial_settings_transaction;
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input [7:0] address;
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input [31:0] data;
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integer x;
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begin
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scl_r <= 1'b1;
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sda_r <= 1'b1;
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@(negedge clk);
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@(negedge clk);
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// Drive SDA low whilst SCL high to signal START
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sda_r <= 1'b0;
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@(negedge clk);
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@(negedge clk);
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// Send 8 Address bits MSB first on falling edge of SCL clocks
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for (x = 7; x >= 0; x = x - 1)
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serial_settings_bit(address[x]);
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// Send 32 Data bits MSB first on falling edge of SCL clocks
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for (x = 31; x >= 0; x = x - 1)
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serial_settings_bit(data[x]);
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// Send STOP.
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scl_r <= 1'b0;
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sda_r <= 1'b0;
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@(negedge clk);
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@(negedge clk);
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@(negedge clk);
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@(negedge clk);
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scl_r <= 1'b1;
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@(negedge clk);
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@(negedge clk);
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@(negedge clk);
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@(negedge clk);
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sda_r <= 1'b1;
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@(negedge clk);
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@(negedge clk);
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@(negedge clk);
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@(negedge clk);
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end
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endtask // serial_settings_transaction
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task serial_settings_bit;
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input one_bit;
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begin
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scl_r <= 1'b0;
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sda_r <= one_bit;
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@(negedge clk);
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@(negedge clk);
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@(negedge clk);
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@(negedge clk);
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scl_r <= 1'b1;
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@(negedge clk);
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@(negedge clk);
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@(negedge clk);
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@(negedge clk);
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end
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endtask // send_settings_bit
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