8f1cfd55b1b5614c510973b7a4c583e683238340
Original-commit: 847b7a631f5e73d732c88a4b4aa91595cf4e4a07
The file is empty.
Languages
Verilog
42.5%
VHDL
13%
SystemVerilog
12%
HTML
11.1%
C
9.6%
Other
11.6%