31 lines
1.1 KiB
Verilog
31 lines
1.1 KiB
Verilog
///////////////////////////////////////////////////////////////////////////////
|
|
// Copyright (c) 2013 Xilinx, Inc.
|
|
// All Rights Reserved
|
|
///////////////////////////////////////////////////////////////////////////////
|
|
// ____ ____
|
|
// / /\/ /
|
|
// /___/ \ / Vendor : Xilinx
|
|
// \ \ \/ Version : 14.4
|
|
// \ \ Application: Xilinx CORE Generator
|
|
// / / Filename : chipscope_ila_128.veo
|
|
// /___/ /\ Timestamp : Tue Oct 22 15:45:46 PDT 2013
|
|
// \ \ / \
|
|
// \___\/\___\
|
|
//
|
|
// Design Name: ISE Instantiation template
|
|
///////////////////////////////////////////////////////////////////////////////
|
|
|
|
// The following must be inserted into your Verilog file for this
|
|
// core to be instantiated. Change the instance name and port connections
|
|
// (in parentheses) to your own signal names.
|
|
|
|
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
|
|
chipscope_ila_128 YourInstanceName (
|
|
.CONTROL(CONTROL), // INOUT BUS [35:0]
|
|
.CLK(CLK), // IN
|
|
.TRIG0(TRIG0) // IN BUS [127:0]
|
|
);
|
|
|
|
// INST_TAG_END ------ End INSTANTIATION Template ---------
|
|
|