85ad83d8d35fd636c1c2e8b5650d0fe8d84eeca1
Original-commit: b63507efb3cf1a8fa20794c452d57028e18da182
The file is empty.
Languages
Verilog
42.5%
VHDL
13%
SystemVerilog
12%
HTML
11.1%
C
9.6%
Other
11.6%