86 lines
2.3 KiB
Verilog
86 lines
2.3 KiB
Verilog
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module catcodec_ddr_cmos
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(
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//output source sync clock for baseband data
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output radio_clk,
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//async reset for clocking
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input arst,
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//control mimo mode
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input mimo,
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//baseband sample interface
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output reg [31:0] rx1,
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output reg [31:0] rx2,
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input [31:0] tx1,
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input [31:0] tx2,
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//capture interface
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input rx_clk,
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input rx_frame,
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input [11:0] rx_d,
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//generate interface
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output tx_clk,
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output tx_frame,
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output [11:0] tx_d
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);
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//rx_clk to DCM - creates codec_clk and codec_clk/2
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wire clk0, clkdv;
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wire locked;
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wire codec_rst = !locked;
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DCM_SP #(
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.CLKDV_DIVIDE(2),
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.CLK_FEEDBACK("1X")
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) DCM_SP_codec_clk
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(
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.RST(arst),
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.CLKIN(rx_clk), .CLKFB(clk0),
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.CLK0(clk0), .CLKDV(clkdv),
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.LOCKED(locked)
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);
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wire codec_clk, half_clk;
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BUFG BUFG_codec_clk(.I(clk0), .O(codec_clk));
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BUFG BUFG_half_clk(.I(clkdv), .O(half_clk));
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BUFGMUX BUFGMUX_radio_clk (.I0(codec_clk), .I1(half_clk), .S(mimo), .O(radio_clk));
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//make codec clock domain mimo mode signal
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reg mimo_r;
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always @(posedge codec_clk) mimo_r <= mimo;
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//assign baseband sample interfaces
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//all samples are registered on strobe
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wire rx_strobe, tx_strobe;
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wire [11:0] rx_i0, rx_q0, rx_i1, rx_q1;
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reg [11:0] tx_i0, tx_q0, tx_i1, tx_q1;
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//tx mux to feed single channel mode from either input
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wire [31:0] txm = (mimo_r || (tx1 != 32'b0))? tx1: tx2;
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always @(posedge codec_clk) begin
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if (rx_strobe) rx2 <= {rx_i1, 4'b0, rx_q1, 4'b0};
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if (rx_strobe) rx1 <= {rx_i0, 4'b0, rx_q0, 4'b0};
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if (tx_strobe) {tx_i0, tx_q0} <= {txm[31:20], txm[15:4]};
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if (tx_strobe) {tx_i1, tx_q1} <= {tx2[31:20], tx2[15:4]};
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end
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// CMOS Data interface to catalina, ignore _n pins
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catcap_ddr_cmos catcap
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(.data_clk(codec_clk), .reset(codec_rst), .mimo(mimo_r),
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.rx_frame(rx_frame), .rx_d(rx_d),
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.rx_clk(/*out*/), .rx_strobe(rx_strobe),
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.i0(rx_i0), .q0(rx_q0),
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.i1(rx_i1), .q1(rx_q1));
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catgen_ddr_cmos catgen
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(.data_clk(tx_clk), .reset(codec_rst), .mimo(mimo_r),
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.tx_frame(tx_frame), .tx_d(tx_d),
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.tx_clk(codec_clk), .tx_strobe(tx_strobe),
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.i0(tx_i0), .q0(tx_q0),
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.i1(tx_i1), .q1(tx_q1));
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endmodule // catcodec_ddr_cmos
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