84 lines
3.8 KiB
Verilog
84 lines
3.8 KiB
Verilog
/*
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-------------------------------------------------------------------------------
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--
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-- File: LvFpga_Chinch_Interface.vhd
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-- Author: Ashish Chaudhari
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-- Original Project: EttusUsrpB250Top
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-- Date: 1 Oct 2013
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--
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-------------------------------------------------------------------------------
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-- (c) 2013 Copyright National Instruments Corporation
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-- All Rights Reserved
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-- National Instruments Internal Information
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--
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-- SPDX-License-Identifier: LGPL-3.0-or-later
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-------------------------------------------------------------------------------
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*/
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`include "LvFpga_Chinch_Interface.vh"
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module LvFpga_Chinch_Interface
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(
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input aIoResetIn_n,
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output bBusReset,
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input BusClk,
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input Rio40Clk,
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input IDelayRefClk,
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input aRioClkPllLocked,
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output aRioClkPllReset,
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output aIoReadyOut,
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input aIoReadyIn,
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output aIoPort2Restart,
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input IoRxClock,
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input IoRxClock_n,
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input [`LVFPGA_IFACE_LINK_WIDTH-1:0] irIoRxData,
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input [`LVFPGA_IFACE_LINK_WIDTH-1:0] irIoRxData_n,
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input irIoRxHeader,
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input irIoRxHeader_n,
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output IoTxClock,
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output IoTxClock_n,
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output [`LVFPGA_IFACE_LINK_WIDTH-1:0] itIoTxData,
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output [`LVFPGA_IFACE_LINK_WIDTH-1:0] itIoTxData_n,
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output itIoTxHeader,
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output itIoTxHeader_n,
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input [(`LVFPGA_IFACE_NUM_RX_DMA_CNT*`LVFPGA_IFACE_DMA_CHAN_WIDTH)-1:0] bDmaRxData,
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input [`LVFPGA_IFACE_NUM_RX_DMA_CNT-1:0] bDmaRxValid,
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output [`LVFPGA_IFACE_NUM_RX_DMA_CNT-1:0] bDmaRxReady,
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output [`LVFPGA_IFACE_NUM_RX_DMA_CNT-1:0] bDmaRxEnabled,
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output [(`LVFPGA_IFACE_NUM_RX_DMA_CNT*`LVFPGA_IFACE_DMA_SIZE_WIDTH)-1:0] bDmaRxFifoFreeCnt,
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output [(`LVFPGA_IFACE_NUM_TX_DMA_CNT*`LVFPGA_IFACE_DMA_CHAN_WIDTH)-1:0] bDmaTxData,
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output [`LVFPGA_IFACE_NUM_TX_DMA_CNT-1:0] bDmaTxValid,
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input [`LVFPGA_IFACE_NUM_TX_DMA_CNT-1:0] bDmaTxReady,
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output [`LVFPGA_IFACE_NUM_TX_DMA_CNT-1:0] bDmaTxEnabled,
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output [(`LVFPGA_IFACE_NUM_TX_DMA_CNT*`LVFPGA_IFACE_DMA_SIZE_WIDTH)-1:0] bDmaTxFifoFullCnt,
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output bUserRegPortInWt,
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output bUserRegPortInRd,
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output [`LVFPGA_IFACE_UREG_ADDR_WIDTH-1:0] bUserRegPortInAddr,
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output [`LVFPGA_IFACE_UREG_DATA_WIDTH-1:0] bUserRegPortInData,
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output [`LVFPGA_IFACE_UREG_SIZE_WIDTH-1:0] bUserRegPortInSize,
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input [`LVFPGA_IFACE_UREG_DATA_WIDTH-1:0] bUserRegPortOutData,
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input bUserRegPortOutDataValid,
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input bUserRegPortOutReady,
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input bChinchRegPortOutWt,
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input bChinchRegPortOutRd,
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input [`LVFPGA_IFACE_CREG_ADDR_WIDTH-1:0] bChinchRegPortOutAddr,
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input [`LVFPGA_IFACE_CREG_DATA_WIDTH-1:0] bChinchRegPortOutData,
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input [`LVFPGA_IFACE_CREG_SIZE_WIDTH-1:0] bChinchRegPortOutSize,
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output [`LVFPGA_IFACE_CREG_DATA_WIDTH-1:0] bChinchRegPortInData,
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output bChinchRegPortInDataValid,
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output bChinchRegPortInReady,
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output aIrq
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) /* synthesis syn_black_box syn_noprune=1 */;
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// This module serves as an API wrapper for LvFpga_Chinch_Interface.ngc and we don't want
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// the tool to accidentally prune out it contents. Hence the syn_black_box syn_noprune=1 directives.
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endmodule
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