61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
135 lines
4.2 KiB
Makefile
135 lines
4.2 KiB
Makefile
#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../../top)
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IP_DIR = $(BASE_DIR)/x400/ip
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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IP_BUILD_DIR = $(BASE_DIR)/x400/build-ip/xczu28drffvg1517-1e
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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# Define part using PART_ID (<device>/<package>/<speedgrade>)
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ARCH = zynquplusRFSOC
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PART_ID = xczu28dr/ffvg1517/-1/e
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# Include makefiles and sources for the DUT and its dependencies
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include $(BASE_DIR)/../lib/control/Makefile.srcs
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include $(BASE_DIR)/../lib/axi/Makefile.srcs
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include $(BASE_DIR)/../lib/axi4_sv/Makefile.srcs
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include $(BASE_DIR)/../lib/axi4s_sv/Makefile.srcs
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include $(BASE_DIR)/../lib/axi4lite_sv/Makefile.srcs
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include $(BASE_DIR)/../lib/packet_proc/Makefile.srcs
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include $(BASE_DIR)/../lib/xge_interface/Makefile.srcs
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include $(BASE_DIR)/../lib/xge/Makefile.srcs
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include $(BASE_DIR)/../lib/wb_spi/Makefile.srcs
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include $(BASE_DIR)/../lib/fifo/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/xport/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/xport_sv/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/crossbar/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
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include $(BASE_DIR)/../lib/xge/Makefile.srcs
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include $(IP_DIR)/Makefile.inc
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IP_AXI_ETH_DMA_BD_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_eth_dma_bd/axi_eth_dma_bd/, \
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sim/axi_eth_dma_bd.v\
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ip/*/sim/*.h\
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ip/*/sim/*.v\
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ip/*/sim/*.vhd\
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ip/*/bd_0/hdl/*.v\
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ip/*/bd_0/sim/*.v\
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ip/*/bd_0/ip/ip_*/sim/*.v\
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ip/*/bd_0/ip/ip_*/sim/*.sv\
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ip/*/bd_0/ip/ip_*/sim/*.vhd\
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ipshared/*/hdl/*.sv\
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ipshared/*/hdl/*.v\
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ipshared/*/simulation/*.v\
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ipshared/*/hdl/verilog/*.v\
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ipshared/*/hdl/verilog/*.svh\
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ipshared/*/hdl/verilog/*.vh\
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))
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IP_AXI_INTERCONNECT_DMA_BD_HDL_SIM_SRCS = $(wildcard $(addprefix $(IP_BUILD_DIR)/axi_interconnect_dma_bd/axi_interconnect_dma_bd/, \
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ip/*/sim/*.v\
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))
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TOP_SRC = \
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$(abspath $(BASE_DIR)/x400/x4xx_qsfp_wrapper.sv) \
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$(abspath $(BASE_DIR)/x400/x4xx_qsfp_wrapper_temp.sv) \
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$(abspath $(BASE_DIR)/x400/x4xx_mgt_io_core.sv) \
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$(abspath $(BASE_DIR)/x400/x4xx.v)
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# Xilinx IP wants lots of libraries
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MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm
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# Needed for the HACK_SRC, speeds up the alignment phase (still long!)
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VLOG_ARGS = +define+SIM_SPEED_UP
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SVLOG_ARGS = -lint +define+BUILD_100G=1
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# Xilinx IP wants a second file loaded
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MODELSIM_ARGS = glbl -t 1fs
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DESIGN_SRCS = $(abspath \
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$(AXI4_SV_SRCS) \
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$(AXI4S_SV_SRCS) \
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$(AXI4LITE_SV_SRCS) \
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$(FIFO_SRCS) \
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$(CONTROL_LIB_SRCS) \
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$(AXI_SRCS) \
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$(XGE_INTERFACE_SRCS) \
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$(PACKET_PROC_SRCS) \
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$(RFNOC_UTIL_SRCS) \
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$(RFNOC_XPORT_SRCS) \
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$(RFNOC_XPORT_SV_SRCS) \
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$(RFNOC_XBAR_SRCS) \
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$(RFNOC_CORE_SRCS) \
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$(WISHBONE_SRCS) \
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$(XGE_SRCS) \
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$(XGE_INTERFACE_SRCS) \
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$(XGE_PCS_PMA_SRCS) \
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$(IP_AXI_ETH_DMA_BD_HDL_SIM_SRCS) \
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$(IP_AXI_INTERCONNECT_DMA_BD_HDL_SIM_SRCS) \
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$(IP_AXI_INTERCONNECT_ETH_HDL_SRCS) \
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$(IP_AXI_INTERCONNECT_DMA_HDL_SRCS) \
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$(IP_AXI_ETH_DMA_BD_HDL_SRCS) \
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$(IP_100G_HDL_SRCS) \
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$(AURORA_PHY_SRCS) \
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$(IP_HDL_SIM_SRCS) \
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$(TOP_SRC) \
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)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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# Define only one toplevel module
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TB_TOP_MODULE ?= x4xx_qsfp_wrapper_all_tb
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SIM_TOP = $(TB_TOP_MODULE)
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SIM_SRCS = \
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$(abspath x4xx_qsfp_wrapper_tb.sv) \
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$(abspath $(TB_TOP_MODULE).sv)
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# Suppressing the following worthless reminder.
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#* Warning: M:/usrp4-hw/oss-repo/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv(228): (vlog-2583) [SVCHK] -
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# Extra checking for conflicts with always_comb and always_latch variables is done at vopt time
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SVLOG_ARGS = -suppress 2583
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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