61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
290 lines
12 KiB
Verilog
290 lines
12 KiB
Verilog
//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: rfdc_timing_control
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//
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// Description:
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//
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// This module handles timed register writes for the RFDC, such as NCO reset
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// control. It takes the CtrlPort master from each radio block and splits it
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// into a CtrlPort bus for the associated daughter board and another CtrlPort
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// bus for the RFDC timing control. Timed commands on the RF timing bus are
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// handled by the ctrlport_timer module.
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//
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// Parameters:
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//
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// NUM_DBOARDS : Number of daughter boards to support
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//
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`default_nettype none
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module rfdc_timing_control #(
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parameter NUM_DBOARDS = 2
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) (
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// Clocks and resets
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input wire clk,
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input wire rst,
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// Time
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input wire [63:0] time_now,
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input wire time_now_stb,
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input wire [ 3:0] time_ignore_bits,
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// CtrlPort Slave (from RFNoC Radio Block)
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input wire [ 1*NUM_DBOARDS-1:0] s_ctrlport_req_wr,
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input wire [ 1*NUM_DBOARDS-1:0] s_ctrlport_req_rd,
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input wire [ 20*NUM_DBOARDS-1:0] s_ctrlport_req_addr,
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input wire [ 32*NUM_DBOARDS-1:0] s_ctrlport_req_data,
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input wire [ 4*NUM_DBOARDS-1:0] s_ctrlport_req_byte_en,
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input wire [ 1*NUM_DBOARDS-1:0] s_ctrlport_req_has_time,
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input wire [ 64*NUM_DBOARDS-1:0] s_ctrlport_req_time,
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output wire [ 1*NUM_DBOARDS-1:0] s_ctrlport_resp_ack,
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output wire [ 2*NUM_DBOARDS-1:0] s_ctrlport_resp_status,
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output wire [ 32*NUM_DBOARDS-1:0] s_ctrlport_resp_data,
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// CtrlPort Master (to Daughter Boards)
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output wire [ 1*NUM_DBOARDS-1:0] m_ctrlport_req_wr,
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output wire [ 1*NUM_DBOARDS-1:0] m_ctrlport_req_rd,
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output wire [ 20*NUM_DBOARDS-1:0] m_ctrlport_req_addr,
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output wire [ 32*NUM_DBOARDS-1:0] m_ctrlport_req_data,
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output wire [ 4*NUM_DBOARDS-1:0] m_ctrlport_req_byte_en,
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output wire [ 1*NUM_DBOARDS-1:0] m_ctrlport_req_has_time,
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output wire [ 64*NUM_DBOARDS-1:0] m_ctrlport_req_time,
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input wire [ 1*NUM_DBOARDS-1:0] m_ctrlport_resp_ack,
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input wire [ 2*NUM_DBOARDS-1:0] m_ctrlport_resp_status,
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input wire [ 32*NUM_DBOARDS-1:0] m_ctrlport_resp_data,
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// RF Reset Control
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output reg start_nco_reset,
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input wire nco_reset_done,
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output reg adc_reset_pulse,
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output reg dac_reset_pulse
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);
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`include "regmap/radio_ctrlport_regmap_utils.vh"
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`include "regmap/rfdc_timing_regmap_utils.vh"
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// Reset registers
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reg [NUM_DBOARDS-1:0] reg_nco_reset_start = 0;
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reg [NUM_DBOARDS-1:0] reg_adc_reset_pulse = 0;
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reg [NUM_DBOARDS-1:0] reg_dac_reset_pulse = 0;
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genvar db;
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generate
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for (db = 0; db < NUM_DBOARDS; db = db+1) begin : gen_db_ctrlport
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//-----------------------------------------------------------------------
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// CtrlPort Splitter
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//-----------------------------------------------------------------------
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wire [ 1-1:0] rf_ctrlport_req_wr;
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wire [ 1-1:0] rf_ctrlport_req_rd;
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wire [ 20-1:0] rf_ctrlport_req_addr;
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wire [ 32-1:0] rf_ctrlport_req_data;
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wire [ 4-1:0] rf_ctrlport_req_byte_en;
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wire [ 1-1:0] rf_ctrlport_req_has_time;
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wire [ 64-1:0] rf_ctrlport_req_time;
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wire [ 1-1:0] rf_ctrlport_resp_ack;
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wire [ 2-1:0] rf_ctrlport_resp_status;
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wire [ 32-1:0] rf_ctrlport_resp_data;
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localparam [31:0] RFDC_TIMING_WINDOW_SIZE_W = $clog2(RFDC_TIMING_WINDOW_SIZE);
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localparam [31:0] DB_WINDOW_SIZE_W = $clog2(DB_WINDOW_SIZE);
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ctrlport_decoder_param #(
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.NUM_SLAVES (2),
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.PORT_BASE ({ RFDC_TIMING_WINDOW[19:0], DB_WINDOW[19:0] }),
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.PORT_ADDR_W ({ RFDC_TIMING_WINDOW_SIZE_W, DB_WINDOW_SIZE_W })
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) ctrlport_decoder_param_i (
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.ctrlport_clk (clk),
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.ctrlport_rst (rst),
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.s_ctrlport_req_wr (s_ctrlport_req_wr [ 1*db+: 1]),
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.s_ctrlport_req_rd (s_ctrlport_req_rd [ 1*db+: 1]),
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.s_ctrlport_req_addr (s_ctrlport_req_addr [20*db+:20]),
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.s_ctrlport_req_data (s_ctrlport_req_data [32*db+:32]),
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.s_ctrlport_req_byte_en (s_ctrlport_req_byte_en [ 4*db+: 4]),
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.s_ctrlport_req_has_time (s_ctrlport_req_has_time [ 1*db+: 1]),
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.s_ctrlport_req_time (s_ctrlport_req_time [64*db+:64]),
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.s_ctrlport_resp_ack (s_ctrlport_resp_ack [ 1*db+: 1]),
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.s_ctrlport_resp_status (s_ctrlport_resp_status [ 2*db+: 2]),
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.s_ctrlport_resp_data (s_ctrlport_resp_data [32*db+:32]),
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.m_ctrlport_req_wr ({ rf_ctrlport_req_wr, m_ctrlport_req_wr [ 1*db+: 1] }),
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.m_ctrlport_req_rd ({ rf_ctrlport_req_rd, m_ctrlport_req_rd [ 1*db+: 1] }),
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.m_ctrlport_req_addr ({ rf_ctrlport_req_addr, m_ctrlport_req_addr [20*db+:20] }),
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.m_ctrlport_req_data ({ rf_ctrlport_req_data, m_ctrlport_req_data [32*db+:32] }),
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.m_ctrlport_req_byte_en ({ rf_ctrlport_req_byte_en, m_ctrlport_req_byte_en [ 4*db+: 4] }),
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.m_ctrlport_req_has_time ({ rf_ctrlport_req_has_time, m_ctrlport_req_has_time [ 1*db+: 1] }),
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.m_ctrlport_req_time ({ rf_ctrlport_req_time, m_ctrlport_req_time [64*db+:64] }),
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.m_ctrlport_resp_ack ({ rf_ctrlport_resp_ack, m_ctrlport_resp_ack [ 1*db+: 1] }),
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.m_ctrlport_resp_status ({ rf_ctrlport_resp_status, m_ctrlport_resp_status [ 2*db+: 2] }),
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.m_ctrlport_resp_data ({ rf_ctrlport_resp_data, m_ctrlport_resp_data [32*db+:32] })
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);
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//-----------------------------------------------------------------------
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// RF Reset Control
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//-----------------------------------------------------------------------
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wire [ 1-1:0] nco_ctrlport_req_wr;
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wire [ 1-1:0] nco_ctrlport_req_rd;
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wire [ 20-1:0] nco_ctrlport_req_addr;
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wire [ 32-1:0] nco_ctrlport_req_data;
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reg [ 1-1:0] nco_ctrlport_resp_ack;
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reg [ 32-1:0] nco_ctrlport_resp_data;
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ctrlport_timer #(
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.EXEC_LATE_CMDS (1)
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) ctrlport_timer_nco (
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.clk (clk),
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.rst (rst),
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.time_now (time_now),
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.time_now_stb (time_now_stb),
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.time_ignore_bits (time_ignore_bits),
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.s_ctrlport_req_wr (rf_ctrlport_req_wr),
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.s_ctrlport_req_rd (rf_ctrlport_req_rd),
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.s_ctrlport_req_addr (rf_ctrlport_req_addr),
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.s_ctrlport_req_data (rf_ctrlport_req_data),
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.s_ctrlport_req_byte_en (rf_ctrlport_req_byte_en),
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.s_ctrlport_req_has_time (rf_ctrlport_req_has_time),
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.s_ctrlport_req_time (rf_ctrlport_req_time),
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.s_ctrlport_resp_ack (rf_ctrlport_resp_ack),
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.s_ctrlport_resp_status (rf_ctrlport_resp_status),
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.s_ctrlport_resp_data (rf_ctrlport_resp_data),
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.m_ctrlport_req_wr (nco_ctrlport_req_wr),
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.m_ctrlport_req_rd (nco_ctrlport_req_rd),
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.m_ctrlport_req_addr (nco_ctrlport_req_addr),
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.m_ctrlport_req_data (nco_ctrlport_req_data),
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.m_ctrlport_req_byte_en (),
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.m_ctrlport_resp_ack (nco_ctrlport_resp_ack),
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.m_ctrlport_resp_status (2'b0),
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.m_ctrlport_resp_data (nco_ctrlport_resp_data)
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);
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always @(posedge clk) begin
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if (rst) begin
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nco_ctrlport_resp_ack <= 0;
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reg_nco_reset_start[db] <= 0;
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nco_ctrlport_resp_data <= 'bX;
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end else begin
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// Default assignments
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reg_nco_reset_start[db] <= 0;
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reg_adc_reset_pulse[db] <= 0;
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reg_dac_reset_pulse[db] <= 0;
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nco_ctrlport_resp_ack <= 0;
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nco_ctrlport_resp_data <= 0;
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// Handle register reads
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if (nco_ctrlport_req_rd) begin
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case (nco_ctrlport_req_addr)
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NCO_RESET_REG: begin
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nco_ctrlport_resp_ack <= 1;
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nco_ctrlport_resp_data[NCO_RESET_DONE] <= nco_reset_done;
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end
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GEARBOX_RESET_REG: begin
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nco_ctrlport_resp_ack <= 1;
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end
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endcase
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end
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// Handle register writes
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if (nco_ctrlport_req_wr) begin
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case (nco_ctrlport_req_addr)
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NCO_RESET_REG: begin
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nco_ctrlport_resp_ack <= 1;
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reg_nco_reset_start[db] <= nco_ctrlport_req_data[NCO_RESET_START];
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end
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GEARBOX_RESET_REG: begin
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nco_ctrlport_resp_ack <= 1;
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reg_adc_reset_pulse[db] <= nco_ctrlport_req_data[ADC_RESET];
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reg_dac_reset_pulse[db] <= nco_ctrlport_req_data[DAC_RESET];
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end
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endcase
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end
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end
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end
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end
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endgenerate
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//---------------------------------------------------------------------------
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// Merge Resets
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//---------------------------------------------------------------------------
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//
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// There are multiple DBs but only one reset signal for each RF component.
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// Since the reset is simply a single cycle pulse, we OR the reset registers
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// for each daughter board together.
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//
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//---------------------------------------------------------------------------
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always @(posedge clk) begin
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if (rst) begin
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start_nco_reset <= 0;
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adc_reset_pulse <= 0;
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dac_reset_pulse <= 0;
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end else begin
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start_nco_reset <= |reg_nco_reset_start;
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adc_reset_pulse <= |reg_adc_reset_pulse;
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dac_reset_pulse <= |reg_dac_reset_pulse;
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end
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end
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endmodule
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`default_nettype wire
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//XmlParse xml_on
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//
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//<regmap name="RADIO_CTRLPORT_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
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// <group name="RADIO_CTRLPORT_WINDOWS">
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// <info>Each radio's CtrlPort peripheral interface is divided into the
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// following memory spaces. Note that the CtrlPort peripheral interface
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// starts at offset 0x80000 in the RFNoC Radio block's register space.</info>
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// <window name="DB_WINDOW" offset="0x00000" size="0x08000">
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// <info>Daughterboard GPIO interface. Register access within this space
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// is directed to the associated daughterboard CPLD.</info>
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// </window>
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// <window name="RFDC_TIMING_WINDOW" offset="0x08000" size="0x08000" targetregmap="RFDC_TIMING_REGMAP">
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// <info>RFDC timing control interface.</info>
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// </window>
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// </group>
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//</regmap>
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//
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//<regmap name="RFDC_TIMING_REGMAP" readablestrobes="false" generatevhdl="true" ettusguidelines="true">
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// <group name="RFDC_TIMING_REGS">
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// <register name="NCO_RESET_REG" offset="0x00" size="32" readable="true" writable="true">
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// <info>NCO reset control register.</info>
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// <bitfield name="NCO_RESET_START" range="0" readable="false" strobe="true">
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// <info>Write a 1 to this bit to start a reset the RFDC's NCO.</info>
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// </bitfield>
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// <bitfield name="NCO_RESET_DONE" range="1" writable="false">
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// <info>When 1, indicates that the NCO reset has completed.</info>
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// </bitfield>
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// </register>
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// <register name="GEARBOX_RESET_REG" offset="0x04" size="32" readable="true" writable="true">
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// <info>Gearbox reset control register.</info>
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// <bitfield name="ADC_RESET" range="0" readable="false" strobe="true">
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// <info>
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// This reset is for the gearbox on the ADC data path that is used to
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// move data from one clock domain to another outside the RFDC. Write
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// a 1 to this bit to send a reset pulse to the ADC gearbox.
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// </info>
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// </bitfield>
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// <bitfield name="DAC_RESET" range="1" readable="false" strobe="true">
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// <info>
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// This reset is for the gearbox on the DAC data path that is used to
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// move data from one clock domain to another outside the RFDC. Write
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// a 1 to this bit to send a reset pulse to the DAC gearbox.
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// </info>
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// </bitfield>
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// </register>
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// </group>
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//</regmap>
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//
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//XmlParse xml_off
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