17 lines
329 B
Verilog
17 lines
329 B
Verilog
//
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// Copyright 2011 Ettus Research LLC
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//
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module add2
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#(parameter WIDTH=16)
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(input [WIDTH-1:0] in1,
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input [WIDTH-1:0] in2,
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output [WIDTH-1:0] sum);
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wire [WIDTH:0] sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2};
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assign sum = sum_int[WIDTH:1]; // Note -- will have some bias
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endmodule // add2
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