8669c68048
Most important effect of this change: rfnoc_image_builder is now required to build bitfiles, 'make' alone won't suffice any longer! This is a huge changeset to the image builder that combines multiple new features: - There no longer is a separate edge file for the static router. The static routes are generated as a Verilog parameter directly into the rfnoc_core_kernel (which is also modified). - image_builder.py is split up into several smaller files. Code is moved into yaml_utils.py, and the new files grc.py, builder_config.py - Generic module support is added. Aside from noc blocks and stream endpoints, we can now instantiate arbitrary modules (they also require a YAML description file). - To enable such modules, resets are now also tracked the same way that clock domains are. - The ImageBuilderConfig config object now more closes matches the original YAML file. The attributes 'clk_domain_con' and 'block_con' are removed. Instead, the attributes 'connections' and 'clk_domains' are sanitized and amended with extra annotations. The templates are updated to reflect this change. - IO ports can now carry parameters, e.g., to have variable wire widths based on the configuration. - Many Pylint warnings were resolved. - Add inheritance support for image core YAML files. This allows image core files to (recursively) inherit from other image core files. To do so, simply put an 'inherit' entry at the top of the file: ```yaml inherit: 'x410_radio_base.yml' ``` - The inheritance feature is used as part of the image core files. - Image core and DTS files are now generated as a build artefact into the build directory. This requires the usage of rfnoc_image_builder to build images. As a consequence, it is no longer required to check in image core Verilog files. - As another consequence, rfnoc_image_builder is required to build bitfiles! - Image flavours are no longer defined through Makefiles, but purely from the image core YAML files. - Remove all image core YAML files that do not generate a shipping image. Because of the inheritance feature and the requirement to use the image builder, it is trivial to add new YAML files. - Add support for transport adapters through the YAML files. Before, transport adapters were inferred from the make target (e.g., X410_X4_200 would have four 10GbE links based on the 'X4' substring). Now, transport adapters are defined via the image core YAML. - This feature is currently only used (or can be used) by the X4xx series. Older devices may or may not be ported to allow custom transport adapters in the future. - Add parameters to the BSP YAMLs and the devices itself. This allows setting global parameters in the image core files. For example, the X4x0 devices use this to decide if they instantiate DRAM channels. - DTS includes and constraint files can now be requested by blocks/transport adapter through their YAML files. They do no longer need to be listed in the Makefile. - Support for secure image cores. These are image cores that allow incorporating RFNoC blocks that require license keys and thus can't live in an open-source environment. This solution adds the option for secure image cores without touching the open source feature set. - Add --reuse option to allow manual editing of generated artefacts - Allow IO signatures from any module: until now IO signatures had to be defined in a single file (io_signatures). This file will persist. In addition each module can add its own IO signature as with the same format the core IO signatures placed under the top level key `io_signatures`. IO signatures are still maintained in a global dictionary. The consequence is that they can be shared among independent modules as well as they have to have a globally unique name. The image builder will warn about detected name clashes for the signatures. - As a consequence, some less commonly used IO signatures were moved to their corresponding module YAML files. Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Lars Amsel <lars.amsel@ni.com> Original-commit: a98ce2621e2a2dc25535fc700b49bfcb00b8eb59
125 lines
4.6 KiB
Makefile
125 lines
4.6 KiB
Makefile
#
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# Copyright 2018 Ettus Research LLC
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#
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# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
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##-------------------
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##USRP E3XX FPGA Help
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##-------------------
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##Usage:
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## make <Targets> <Options>
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##
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##Output:
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## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header
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## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.dts: Device tree source file
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## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary)
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# Base output directory for all builds.
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BUILD_BASE_DIR ?= .
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# Base directory for the build outputs.
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BUILD_OUTPUT_DIR ?= $(BUILD_BASE_DIR)/build
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# Initialize a build seed. This can be changed to randomly affect build results.
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BUILD_SEED ?= 0
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DEFS += BUILD_SEED=$(BUILD_SEED)
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# Set build option (check RTL, run synthesis, or do a full build)
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ifndef TARGET
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ifeq ($(CHECK), 1)
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TARGET = rtl
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else ifeq ($(SYNTH), 1)
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TARGET = synth
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else ifeq ($(IP_ONLY), 1)
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TARGET = viv_ip
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else
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TARGET = bin
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endif
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endif
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TOP ?= e31x
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DEFAULT_IMAGE_CORE_FILE_E31X=e310_rfnoc_image_core.v
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# vivado_build($1=Device, $2=Definitions)
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vivado_build = make -f Makefile.e31x.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_E31X)
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vivado_ip = make -f Makefile.e31x.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2" DEFAULT_RFNOC_IMAGE_CORE_FILE=$(DEFAULT_IMAGE_CORE_FILE_E31X)
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# post_build($1=Device, $2=Option)
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ifeq ($(TARGET),bin)
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post_build = @\
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mkdir -p $(BUILD_OUTPUT_DIR); \
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echo "Exporting bitstream file..."; \
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cp $(BUILD_BASE_DIR)/build-$(1)/e31x.bit $(BUILD_OUTPUT_DIR)/usrp_`echo $(2) | tr A-Z a-z`_fpga.bit; \
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echo "Exporting build report..."; \
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cp $(BUILD_BASE_DIR)/build-$(1)/build.rpt $(BUILD_OUTPUT_DIR)/usrp_`echo $(2) | tr A-Z a-z`_fpga.rpt; \
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echo "Build DONE ... $(1)";
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else
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post_build = @echo "Skipping bitfile export."
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endif
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##
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##Supported Targets
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##-----------------
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all: E310_SG1_IDLE E310_SG3_IDLE E310_SG1 E310_SG3 ##(Default target)
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##E310_SG1_IP: Build IP for E310_SG1 only.
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E310_SG1_IP:
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+$(call vivado_ip,E310_SG1,E310_SG1=1)
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##E310_SG3_IP: Build IP for E310_SG3 only.
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E310_SG3_IP:
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+$(call vivado_ip,E310_SG3,E310_SG3=1)
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##E310_SG1_IDLE: Build USRP E3XX idle design (Speed Grade 1).
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E310_SG1_IDLE E3XX_idle: E310_SG1_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg1_idle_fpga.dts
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$(call vivado_build,E310_SG1,$(DEFS) E310_IDLE_IMAGE=1 E310_SG1=1)
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$(call post_build,$@,E310_SG1_IDLE)
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##E310_SG3_IDLE: Build USRP E3XX idle design (Speed Grade 3).
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E310_SG3_IDLE E3XX_idle_sg3: E310_SG3_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg3_idle_fpga.dts
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$(call vivado_build,E310_SG3,$(DEFS) E310_IDLE_IMAGE=1 E310_SG3=1)
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$(call post_build,$@,E310_SG3_IDLE)
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##E310_SG1: Build USRP E3XX (Speed Grade 1).
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E310_SG1 E310: E310_SG1_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg1_fpga.dts
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$(call vivado_build,E310_SG1,$(DEFS) E310_SG1=1 $(if $(DRAM),ENABLE_DRAM=1,))
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$(call post_build,$@,E310_SG1)
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##E310_SG3: Build USRP E3XX (Speed Grade 3).
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E310_SG3 E310_sg3: E310_SG3_IP $(BUILD_OUTPUT_DIR)/usrp_e310_sg3_fpga.dts
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$(call vivado_build,E310_SG3,$(DEFS) E310_SG3=1 $(if $(DRAM),ENABLE_DRAM=1,))
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$(call post_build,$@,E310_SG3)
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$(BUILD_OUTPUT_DIR)/%.dts: dts/%.dts dts/*.dtsi
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-mkdir -p $(BUILD_OUTPUT_DIR)
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${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $<
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clean: ##Clean up all target build outputs.
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@echo "Cleaning targets..."
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@rm -rf $(BUILD_BASE_DIR)/build-E3*
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@rm -rf $(BUILD_OUTPUT_DIR)
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cleanall: ##Clean up all target and ip build outputs.
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@echo "Cleaning targets and IP..."
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@rm -rf build-ip
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@rm -rf $(BUILD_BASE_DIR)/build-E3*
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@rm -rf $(BUILD_OUTPUT_DIR)
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help: ##Show this help message.
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@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
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##
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##Supported Options
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##-----------------
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##DRAM=1 Include DDR3 SDRAM memory controller IP in the FPGA build.
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## Note: The RFNoC image core must also be configured to use DRAM.
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##GUI=1 Launch the build in the Vivado GUI.
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##PROJECT=1 Save Vivado project file, otherwise it's created in memory.
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##CHECK=1 Launch the syntax checker instead of building a bitfile.
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##IP_ONLY=1 Launch the build but stop after IP generation.
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##SYNTH=1 Launch the build but stop after synthesis.
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##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0)
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##TOP=<module> Specify a top module for syntax checking. (Default is the bitfile top)
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.PHONY: all clean cleanall help
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