42 lines
1005 B
Verilog
42 lines
1005 B
Verilog
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`define LOG2(N) (\
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N < 2 ? 0 : \
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N < 4 ? 1 : \
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N < 8 ? 2 : \
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N < 16 ? 3 : \
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N < 32 ? 4 : \
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N < 64 ? 5 : \
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N < 128 ? 6 : \
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N < 256 ? 7 : \
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N < 512 ? 8 : \
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N < 1024 ? 9 : \
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10)
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module binary_encoder
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#(
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parameter SIZE = 16
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)
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(
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input [SIZE-1:0] in,
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output [`LOG2(SIZE)-1:0] out
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);
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genvar m,n;
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generate
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// Loop enough times to represent the total number of input bits as an encoded value
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for (m = 0; m <= `log2(SIZE-1); m = m + 1) begin: expand_or_tree
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wire [SIZE-1:0] encoding;
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// Build enable mask by iterating through every input bit.
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for (n = 0; n < SIZE ; n = n + 1) begin: encode_this_bit
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assign encoding[n] = n[m];
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end
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// OR tree for this output bit with appropraite bits enabled.
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assign out[m] = |(encoding & in);
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end
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endgenerate
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endmodule // binary_encoder
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