65d3d1eabd86dbd014a1935b6b94d6d5cfa42a51
Original-commit: 09882ad86432db5087f85764c02989dbfc70fd3f
The file is empty.
Languages
Verilog
42.5%
VHDL
13%
SystemVerilog
12%
HTML
11.1%
C
9.6%
Other
11.6%