miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
6386d90b35612766e23d166e6371c7d3547fb80f
b210-k7-fpga/lib/vita_200
T
History
michael-west 5983927439 sim: Update chdr_16sc_to_sc12 testbench 
Modified to send 2 packets back to back at each packet size to test
output during sequential input packets.  Also fixed whitespace.

Signed-off-by: michael-west <michael.west@ettus.com>


Original-commit: 439770b964be45e6160cf99a0b1551fdd2002fa9
2021-08-10 15:19:32 -05:00
..
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build_8_to_16
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build_12_to_16
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build_16_to_8
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build_16_to_12
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_8s_to_16s.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_8sc_to_16sc_tb.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_8sc_to_16sc.hex
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_8sc_to_16sc.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_12sc_to_16sc_tb.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_12sc_to_16sc.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_16s_to_8s.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_16s_to_32f.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_16sc_to_8sc_tb.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_16sc_to_8sc.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_16sc_to_12sc_tb.v
sim: Update chdr_16sc_to_sc12 testbench
2021-08-10 15:19:32 -05:00
chdr_16sc_to_12sc.v
fpga: Fix sc16 to sc12 converter
2021-08-10 15:19:32 -05:00
chdr_16sc_to_32f_tb.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_16sc_to_32f.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_16sc_to_xxxx_chain.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_32f_to_16s.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_32f_to_16sc_tb.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_32f_to_16sc.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_xxxx_to_16sc_chain.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
context_packet_gen.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
float_to_iq_tb.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
float_to_iq.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
from8_to_x.hex
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
from12_to_x.hex
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
from16_to_x.hex
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
generate_bits.cpp
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
iq_to_float_input.txt
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
iq_to_float_output.txt
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
iq_to_float_tb.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
iq_to_float.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile.srcs
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
new_rx_control.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
new_rx_framer.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
new_rx_tb.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
new_tx_control_tb.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
new_tx_control.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
new_tx_deframer.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
new_tx_tb.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
trigger_context_pkt.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
tx_responder.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
xxf_to_xxs.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
xxs_to_xxf.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00