421 lines
15 KiB
Verilog
421 lines
15 KiB
Verilog
//
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// Copyright 2018 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: n3xx_mgt_channel_wrapper
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//
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// Description:
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//
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// Aurora/10 GbE wrapper for up to 4 QSFP lanes -or-
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// Aurora/1 GbE/10 GbE/White Rabbit wrapper for 1 SFP+ lane
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//
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// Parameters:
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//
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// PROTOCOL : Must be {10GbE, Aurora, Disabled}
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// LANES : Number of lanes of to instantiate (1, 2, 3, or 4)
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// REG_BASE : Base register address
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// PORTNUM_BASE : Base port number for discovery
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// MDIO_EN : Enable MDIO port
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// MDIO_PHYADDR : MDIO address to use
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// REG_DWIDTH : Width of regport address bus
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// REG_AWIDTH : Width of regport data bus
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// GT_COMMON : Use GT Common ports on MGT
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// BYTE_MTU : Log base 2 of the MTU size in bytes
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// RFNOC_PROTOVER : RFNoC protocol version to be reported by transport
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// adapters.
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// NODE_INST : RFNoC transport adapter node instance for this port
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//
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`default_nettype none
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module n3xx_mgt_channel_wrapper #(
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parameter PROTOCOL = "10GbE",
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parameter LANES = 2,
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parameter REG_BASE = 32'h0,
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parameter PORTNUM_BASE = 4,
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parameter MDIO_EN = 1,
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parameter [ 4:0] MDIO_PHYADDR = 5'd0,
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parameter REG_DWIDTH = 32,
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parameter REG_AWIDTH = 14,
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parameter GT_COMMON = 1,
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parameter BYTE_MTU = $clog2(8192),
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parameter [15:0] RFNOC_PROTOVER = {8'd1, 8'd0},
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parameter NODE_INST_BASE = 0
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)(
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// Resets
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input wire areset,
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input wire bus_rst,
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// Clocks
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input wire gt_refclk,
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input wire gb_refclk,
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input wire misc_clk,
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input wire bus_clk,
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input wire user_clk,
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input wire sync_clk,
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//Axi-lite
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input wire s_axi_aclk,
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input wire s_axi_aresetn,
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input wire [REG_AWIDTH-1:0] s_axi_awaddr,
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input wire s_axi_awvalid,
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output wire s_axi_awready,
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input wire [REG_DWIDTH-1:0] s_axi_wdata,
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input wire [REG_DWIDTH/8-1:0] s_axi_wstrb,
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input wire s_axi_wvalid,
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output wire s_axi_wready,
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output wire [1:0] s_axi_bresp,
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output wire s_axi_bvalid,
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input wire s_axi_bready,
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input wire [REG_AWIDTH-1:0] s_axi_araddr,
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input wire s_axi_arvalid,
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output wire s_axi_arready,
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output wire [REG_DWIDTH-1:0] s_axi_rdata,
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output wire [1:0] s_axi_rresp,
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output wire s_axi_rvalid,
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input wire s_axi_rready,
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// Serial lanes (high-speed IO)
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output wire [LANES-1:0] txp,
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output wire [LANES-1:0] txn,
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input wire [LANES-1:0] rxp,
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input wire [LANES-1:0] rxn,
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// Low-speed IO (QSFP+ and SFP+ module signals)
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input wire mod_present_n,
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input wire mod_rxlos,
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input wire mod_tx_fault,
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output wire mod_tx_disable,
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input wire mod_reset_n,
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input wire mod_int_n,
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output wire mod_lpmode,
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output wire mod_sel_n,
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// Timebase Outputs
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output wire mod_pps,
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output wire mod_refclk,
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// GT Common
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output wire qpllreset,
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input wire qplllock,
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input wire qplloutclk,
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input wire qplloutrefclk,
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input wire qpllrefclklost,
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// Aurora MMCM
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input wire mmcm_locked,
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output wire gt_pll_lock,
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output wire gt_tx_out_clk_unbuf,
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// AXIS output interface
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output wire [(LANES*64)-1:0] e2v_tdata,
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output wire [LANES-1:0] e2v_tlast,
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output wire [LANES-1:0] e2v_tvalid,
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input wire [LANES-1:0] e2v_tready,
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// AXIS input interface
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input wire [(LANES*64)-1:0] v2e_tdata,
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input wire [LANES-1:0] v2e_tlast,
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input wire [LANES-1:0] v2e_tvalid,
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output wire [LANES-1:0] v2e_tready,
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// CPU
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output wire [LANES*64-1:0] e2c_tdata,
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output wire [LANES*8-1:0] e2c_tkeep,
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output wire [LANES-1:0] e2c_tlast,
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output wire [LANES-1:0] e2c_tvalid,
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input wire [LANES-1:0] e2c_tready,
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input wire [LANES*64-1:0] c2e_tdata,
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input wire [LANES*8-1:0] c2e_tkeep,
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input wire [LANES-1:0] c2e_tlast,
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input wire [LANES-1:0] c2e_tvalid,
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output wire [LANES-1:0] c2e_tready,
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// MISC
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output wire [LANES*32-1:0] port_info,
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input wire [15:0] device_id,
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// Sideband White Rabbit Control
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input wire wr_reset_n,
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input wire wr_refclk,
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output wire wr_dac_sclk,
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output wire wr_dac_din,
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output wire wr_dac_clr_n,
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output wire wr_dac_cs_n,
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output wire wr_dac_ldac_n,
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output wire wr_eeprom_scl_o,
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input wire wr_eeprom_scl_i,
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output wire wr_eeprom_sda_o,
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input wire wr_eeprom_sda_i,
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input wire wr_uart_rx,
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output wire wr_uart_tx,
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// WR AXI Control
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output wire wr_axi_aclk,
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input wire wr_axi_aresetn,
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input wire [31:0] wr_axi_awaddr,
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input wire wr_axi_awvalid,
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output wire wr_axi_awready,
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input wire [REG_DWIDTH-1:0] wr_axi_wdata,
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input wire [REG_DWIDTH/8-1:0] wr_axi_wstrb,
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input wire wr_axi_wvalid,
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output wire wr_axi_wready,
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output wire [1:0] wr_axi_bresp,
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output wire wr_axi_bvalid,
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input wire wr_axi_bready,
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input wire [31:0] wr_axi_araddr,
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input wire wr_axi_arvalid,
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output wire wr_axi_arready,
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output wire [REG_DWIDTH-1:0] wr_axi_rdata,
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output wire [1:0] wr_axi_rresp,
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output wire wr_axi_rvalid,
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input wire wr_axi_rready,
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output wire wr_axi_rlast,
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output wire [LANES-1:0] link_up,
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output wire [LANES-1:0] activity
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);
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//--------------------------------------------------------------
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// QSFP module I/O
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//--------------------------------------------------------------
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assign mod_reset_n = 1'b1;
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assign mod_sel_n = 1'b0;
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assign mod_lpmode = 1'b0;
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//--------------------------------------------------------------
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// Common clocking
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//--------------------------------------------------------------
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wire [LANES-1:0] qpllreset_ln;
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wire [LANES-1:0] gt_tx_out_clk;
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wire [LANES-1:0] gt_pll_lock_ln;
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assign qpllreset = |qpllreset_ln;
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assign gt_tx_out_clk_unbuf = gt_tx_out_clk[0];
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assign gt_pll_lock = gt_pll_lock_ln[0];
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//--------------------------------------------------------------
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// Register bus
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//--------------------------------------------------------------
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localparam REG_BLOCK_SIZE = 20'h4000;
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// AXI4-Lite to RegPort (PS to PL Register Access)
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wire reg_wr_req;
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wire [REG_AWIDTH-1:0] reg_wr_addr;
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wire [REG_DWIDTH-1:0] reg_wr_data;
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wire reg_rd_req;
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wire [REG_AWIDTH-1:0] reg_rd_addr;
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wire reg_rd_resp;
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wire [REG_DWIDTH-1:0] reg_rd_data;
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axil_regport_master #(
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.DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64)
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.AWIDTH (REG_AWIDTH), // Width of the address bus
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.WRBASE (0), // Write address base
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.RDBASE (0), // Read address base
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.TIMEOUT (10) // log2(timeout). Read will timeout after (2^TIMEOUT - 1) cycles
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) mgt_reg_mst_i (
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// Clock and reset
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.s_axi_aclk (s_axi_aclk),
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.s_axi_aresetn (s_axi_aresetn),
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// AXI4-Lite: Write address port (domain: s_axi_aclk)
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.s_axi_awaddr (s_axi_awaddr),
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.s_axi_awvalid (s_axi_awvalid),
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.s_axi_awready (s_axi_awready),
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// AXI4-Lite: Write data port (domain: s_axi_aclk)
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.s_axi_wdata (s_axi_wdata),
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.s_axi_wstrb (s_axi_wstrb),
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.s_axi_wvalid (s_axi_wvalid),
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.s_axi_wready (s_axi_wready),
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// AXI4-Lite: Write response port (domain: s_axi_aclk)
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.s_axi_bresp (s_axi_bresp),
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.s_axi_bvalid (s_axi_bvalid),
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.s_axi_bready (s_axi_bready),
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// AXI4-Lite: Read address port (domain: s_axi_aclk)
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.s_axi_araddr (s_axi_araddr),
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.s_axi_arvalid (s_axi_arvalid),
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.s_axi_arready (s_axi_arready),
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// AXI4-Lite: Read data port (domain: s_axi_aclk)
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.s_axi_rdata (s_axi_rdata),
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.s_axi_rresp (s_axi_rresp),
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.s_axi_rvalid (s_axi_rvalid),
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.s_axi_rready (s_axi_rready),
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// Register port: Write port (domain: reg_clk)
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.reg_clk (bus_clk),
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.reg_wr_req (reg_wr_req),
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.reg_wr_addr (reg_wr_addr),
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.reg_wr_data (reg_wr_data),
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.reg_wr_keep (/*unused*/),
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// Register port: Read port (domain: reg_clk)
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.reg_rd_req (reg_rd_req),
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.reg_rd_addr (reg_rd_addr),
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.reg_rd_resp (reg_rd_resp),
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.reg_rd_data (reg_rd_data)
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);
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wire [LANES-1:0] reg_rd_resp_flat;
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wire [(LANES*REG_DWIDTH)-1:0] reg_rd_data_flat;
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wire [LANES-1:0] mod_pps_flat;
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wire [LANES-1:0] mod_refclk_flat;
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// NOTE: Connecting WR signals of first lane only
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assign mod_pps = mod_pps_flat[0];
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assign mod_refclk = mod_refclk_flat[0];
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regport_resp_mux #(
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.WIDTH (REG_DWIDTH),
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.NUM_SLAVES (LANES)
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) reg_resp_mux_i(
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.clk(bus_clk), .reset(bus_rst),
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.sla_rd_resp(reg_rd_resp_flat), .sla_rd_data(reg_rd_data_flat),
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.mst_rd_resp(reg_rd_resp), .mst_rd_data(reg_rd_data)
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);
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//--------------------------------------------------------------
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// Lanes
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//--------------------------------------------------------------
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genvar l;
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generate
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for (l = 0; l < LANES; l = l + 1) begin: lanes
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n3xx_mgt_wrapper #(
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.PROTOCOL (PROTOCOL),
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.REG_BASE (REG_BASE + (REG_BLOCK_SIZE * l)),
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.REG_DWIDTH (REG_DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64)
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.REG_AWIDTH (REG_AWIDTH), // Width of the address bus
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.GT_COMMON (GT_COMMON),
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.MDIO_EN (MDIO_EN),
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.MDIO_PHYADDR (MDIO_PHYADDR),
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.BYTE_MTU (BYTE_MTU),
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.RFNOC_PROTOVER (RFNOC_PROTOVER),
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.PORTNUM (PORTNUM_BASE + l),
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.NODE_INST (NODE_INST_BASE + l)
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) lane_i (
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//must reset all channels on quad when sfp1 gtx core is reset
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.areset (areset),
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.gt_refclk (gt_refclk),
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.gb_refclk (gb_refclk),
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.misc_clk (misc_clk),
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.user_clk (user_clk),
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.sync_clk (sync_clk),
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.bus_rst (bus_rst),
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.bus_clk (bus_clk),
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//RegPort
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.reg_wr_req (reg_wr_req),
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.reg_wr_addr (reg_wr_addr),
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.reg_wr_data (reg_wr_data),
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.reg_rd_req (reg_rd_req),
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.reg_rd_addr (reg_rd_addr),
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.reg_rd_resp (reg_rd_resp_flat[l]),
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.reg_rd_data (reg_rd_data_flat[l*REG_DWIDTH +: REG_DWIDTH]),
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.txp (txp[l]),
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.txn (txn[l]),
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.rxp (rxp[l]),
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.rxn (rxn[l]),
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.mod_present_n (mod_present_n),
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.mod_rxlos (mod_rxlos),
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.mod_tx_fault (mod_tx_fault),
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.mod_tx_disable (mod_tx_disable),
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.qpllrefclklost (qpllrefclklost),
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.qplllock (qplllock),
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.qplloutclk (qplloutclk),
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.qplloutrefclk (qplloutrefclk),
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.qpllreset (qpllreset_ln[l]),
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.mmcm_locked (mmcm_locked),
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.gt_pll_lock (gt_pll_lock_ln[l]),
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.gt_tx_out_clk_unbuf(gt_tx_out_clk[l]),
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// Vita router interface (Synchronous to bus_clk)
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.e2v_tdata (e2v_tdata[l*64 +: 64]),
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.e2v_tlast (e2v_tlast[l]),
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.e2v_tvalid (e2v_tvalid[l]),
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.e2v_tready (e2v_tready[l]),
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.v2e_tdata (v2e_tdata[l*64 +: 64]),
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.v2e_tlast (v2e_tlast[l]),
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.v2e_tvalid (v2e_tvalid[l]),
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.v2e_tready (v2e_tready[l]),
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// CPU
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.e2c_tdata (e2c_tdata[l*64 +: 64]),
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.e2c_tkeep (e2c_tkeep[l*8 +: 8]),
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.e2c_tlast (e2c_tlast[l]),
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.e2c_tvalid (e2c_tvalid[l]),
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.e2c_tready (e2c_tready[l]),
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.c2e_tdata (c2e_tdata[l*64 +: 64]),
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.c2e_tkeep (c2e_tkeep[l*8 +: 8]),
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.c2e_tlast (c2e_tlast[l]),
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.c2e_tvalid (c2e_tvalid[l]),
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.c2e_tready (c2e_tready[l]),
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.port_info (port_info[l*32 +: 32]),
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.device_id (device_id),
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// Timebase Outputs
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.mod_pps(mod_pps_flat[l]),
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.mod_refclk(mod_refclk_flat[l]),
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// Sideband White Rabbit Control
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.wr_reset_n (wr_reset_n),
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.wr_refclk (wr_refclk),
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.wr_dac_sclk (wr_dac_sclk),
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.wr_dac_din (wr_dac_din),
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.wr_dac_clr_n (wr_dac_clr_n),
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.wr_dac_cs_n (wr_dac_cs_n),
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.wr_dac_ldac_n (wr_dac_ldac_n),
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.wr_eeprom_scl_o(wr_eeprom_scl_o),
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.wr_eeprom_scl_i(wr_eeprom_scl_i),
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.wr_eeprom_sda_o(wr_eeprom_sda_o),
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.wr_eeprom_sda_i(wr_eeprom_sda_o),
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.wr_uart_rx (wr_uart_rx),
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.wr_uart_tx (wr_uart_tx),
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// WR AXI Control
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.wr_axi_aclk (wr_axi_aclk),
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.wr_axi_aresetn (wr_axi_aresetn),
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.wr_axi_awaddr (wr_axi_awaddr),
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.wr_axi_awvalid (wr_axi_awvalid),
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.wr_axi_awready (wr_axi_awready),
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.wr_axi_wdata (wr_axi_wdata),
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.wr_axi_wstrb (wr_axi_wstrb),
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.wr_axi_wvalid (wr_axi_wvalid),
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.wr_axi_wready (wr_axi_wready),
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.wr_axi_bresp (wr_axi_bresp),
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.wr_axi_bvalid (wr_axi_bvalid),
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.wr_axi_bready (wr_axi_bready),
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.wr_axi_araddr (wr_axi_araddr),
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.wr_axi_arvalid (wr_axi_arvalid),
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.wr_axi_arready (wr_axi_arready),
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.wr_axi_rdata (wr_axi_rdata),
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.wr_axi_rresp (wr_axi_rresp),
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.wr_axi_rvalid (wr_axi_rvalid),
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.wr_axi_rready (wr_axi_rready),
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.wr_axi_rlast (wr_axi_rlast),
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.link_up (link_up[l]),
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.activity (activity[l])
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);
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end
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endgenerate
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endmodule
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`default_nettype wire
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