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600df8752c6902dc24e9943c9873e8082553adff
b210-k7-fpga/top/n3xx
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Wade Fife 600df8752c fpga: Add option to build IP only 
Original-commit: adcca0acd995a75fb2dede4d6a86641821e49e3d
2024-03-15 20:07:28 -05:00
..
coregen_dsp
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dboards
fpga: n3xx: Add CE clock
2023-10-18 22:23:55 -05:00
doc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dts
fpga: n320: Add BIST (AA) image files
2020-07-31 14:32:54 -05:00
ip
fpga: Use AR76780 patch for fir_compiler
2022-08-25 13:55:30 -05:00
sim
fpga: n3xx: Upgrade to Vivado 2021.1
2022-08-25 13:55:30 -05:00
.gitignore
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
build_n3xx.tcl
fpga: Add incremental to strategies for e3xx, n3xx, x3xx
2024-03-14 16:35:11 -05:00
dev_config.json
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile
fpga: Add option to build IP only
2024-03-15 20:07:28 -05:00
Makefile.n3xx.inc
fpga: Fix RFNoC OOT Makefile inclusion
2023-07-26 15:13:50 -05:00
mb_clocks.xdc
fpga: n3xx: Add CE clock
2023-10-18 22:23:55 -05:00
mb_pins.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
mb_timing.xdc
fpga: n3xx: Fix async clocks relationship
2022-08-25 13:55:30 -05:00
n3xx_clocking.v
n3xx: Add comments on clock_source=external,time_source=gpsdo
2024-02-21 06:40:57 -06:00
n3xx_core.v
fpga: n3xx: Add CE clock
2023-10-18 22:23:55 -05:00
n3xx_db_fe_core.v
fpga: Update copyright
2023-01-19 15:55:56 -08:00
n3xx_mgt_channel_wrapper.v
fpga: n3xx: Cleanup MTU parameters
2022-09-01 14:41:55 -05:00
n3xx_mgt_io_core.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_mgt_wrapper.v
fpga: n3xx: Cleanup MTU parameters
2022-09-01 14:41:55 -05:00
n3xx_serial_dac_arb.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_serial_dac.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_wr_top.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n3xx_wr.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n300_bist_rfnoc_image_core.v
fpga: n3xx: Rename BIST image cores
2024-03-15 00:32:53 -05:00
n300_bist_rfnoc_image_core.vh
fpga: n3xx: Rename BIST image cores
2024-03-15 00:32:53 -05:00
n300_bist_rfnoc_image_core.yml
fpga: n3xx: Rename BIST image cores
2024-03-15 00:32:53 -05:00
n300_bist_static_router.hex
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n300_rfnoc_image_core.v
fpga: n3xx: Add CE clock
2023-10-18 22:23:55 -05:00
n300_rfnoc_image_core.vh
fpga: Update all RFNoC image core files
2023-02-24 08:07:17 -06:00
n300_rfnoc_image_core.yml
fpga: Update RFNoC YAML copyright
2023-02-22 21:55:02 -06:00
n300_static_router.hex
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
n310_1ge.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_10ge.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_aurora.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_bist_rfnoc_image_core.v
fpga: n3xx: Rename BIST image cores
2024-03-15 00:32:53 -05:00
n310_bist_rfnoc_image_core.vh
fpga: n3xx: Rename BIST image cores
2024-03-15 00:32:53 -05:00
n310_bist_rfnoc_image_core.yml
fpga: n3xx: Rename BIST image cores
2024-03-15 00:32:53 -05:00
n310_bist_static_router.hex
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_dram.xdc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
n310_rfnoc_image_core.v
fpga: n3xx: Add CE clock
2023-10-18 22:23:55 -05:00
n310_rfnoc_image_core.vh
fpga: Update all RFNoC image core files
2023-02-24 08:07:17 -06:00
n310_rfnoc_image_core.yml
fpga: Update RFNoC YAML copyright
2023-02-22 21:55:02 -06:00
n310_static_router.hex
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
n320_bist_rfnoc_image_core.v
fpga: n3xx: Rename BIST image cores
2024-03-15 00:32:53 -05:00
n320_bist_rfnoc_image_core.vh
fpga: n3xx: Rename BIST image cores
2024-03-15 00:32:53 -05:00
n320_bist_rfnoc_image_core.yml
fpga: n3xx: Rename BIST image cores
2024-03-15 00:32:53 -05:00
n320_bist_static_router.hex
fpga: n320: Add BIST (AA) image files
2020-07-31 14:32:54 -05:00
n320_rfnoc_image_core.v
fpga: n3xx: Add CE clock
2023-10-18 22:23:55 -05:00
n320_rfnoc_image_core.vh
fpga: Update all RFNoC image core files
2023-02-24 08:07:17 -06:00
n320_rfnoc_image_core.yml
fpga: n3xx: Add CE clock
2023-10-18 22:23:55 -05:00
n320_static_router.hex
fpga: Add Replay Block to RFNoC Core Image
2020-09-03 15:26:33 -05:00
setupenv.sh
fpga: Use AR76780 patch for fir_compiler
2022-08-25 13:55:30 -05:00
WrapBufg.vhd
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00