Ashish Chaudhari
adf2da6ac7
- Fixed 10GigE firmware communication issues and sequence errors for TX - Multiple changes to help ease timing closure - Cleaned up build scripts - Switched to Xilinx ISE 14.7 as the default build tool for X300 Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0
326 lines
9.8 KiB
Verilog
326 lines
9.8 KiB
Verilog
//
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// Copyright 2013 Ettus Research LLC
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//
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//
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// Wrap XGE MAC so that:
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//
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// *) Signals are crossed between the MAC's own 156.25MHz clock domain and the
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// main FPGA clock domain.
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// *) 6 byte Padding is added at RX, including metadata so that IP headers become aligned.
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// *) 6 Byte padding is stripped at TX, so that Eth header data starts immediately.
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// *) TX & RX can buffer at least an MTU sized packet
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// *) On TX, to not start an Ethernet Tx until a complete packet is present in the
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// last Tx FIFO so that the MAC doesn't underrun.
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//
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module xge_mac_wrapper
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#(parameter PORTNUM=8'd0)
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(
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// XGMII
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input xgmii_clk,
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output [63:0] xgmii_txd,
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output [7:0] xgmii_txc,
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input [63:0] xgmii_rxd,
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input [7:0] xgmii_rxc,
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// MDIO
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output mdc,
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output mdio_in,
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input mdio_out,
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// Wishbone I/F
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input [7:0] wb_adr_i, // To wishbone_if0 of wishbone_if.v
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input wb_clk_i, // To sync_clk_wb0 of sync_clk_wb.v, ...
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input wb_cyc_i, // To wishbone_if0 of wishbone_if.v
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input [31:0] wb_dat_i, // To wishbone_if0 of wishbone_if.v
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input wb_rst_i, // To sync_clk_wb0 of sync_clk_wb.v, ...
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input wb_stb_i, // To wishbone_if0 of wishbone_if.v
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input wb_we_i, // To wishbone_if0 of wishbone_if.v
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output wb_ack_o, // From wishbone_if0 of wishbone_if.v
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output [31:0] wb_dat_o, // From wishbone_if0 of wishbone_if.v
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output wb_int_o, // From wishbone_if0 of wishbone_if.v
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// Client FIFO Interfaces
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input sys_clk,
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input reset, // From sys_clk domain.
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output [63:0] rx_tdata,
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output [3:0] rx_tuser,
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output rx_tlast,
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output rx_tvalid,
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input rx_tready,
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input [63:0] tx_tdata,
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input [3:0] tx_tuser, // Bit[3] (error) is ignored for now.
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input tx_tlast,
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input tx_tvalid,
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output tx_tready,
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// Other
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input phy_ready,
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// Debug
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output [31:0] debug_rx,
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output [31:0] debug_tx);
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(* ASYNC_REG = "TRUE" *)
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reg xgmii_reset_r1;
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reg xgmii_reset;
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//
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// Generate 156MHz synchronized reset localy
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//
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always @(posedge xgmii_clk or posedge reset)
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begin
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if (reset) begin
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xgmii_reset_r1 <= 1'b1;
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xgmii_reset <= 1'b1;
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end
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else begin
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xgmii_reset_r1 <= 1'b0; // IJB. Was PLL lock here.
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xgmii_reset <= xgmii_reset_r1;
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end
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end // always @ (posedge xgmii_clk or posedge reset)
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//
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// 10G MAC
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//
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wire [63:0] eth_rx_data;
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wire eth_rx_avail;
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wire eth_rx_eof;
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wire eth_rx_err;
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wire [2:0] eth_rx_occ;
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wire eth_rx_sof;
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wire eth_rx_valid;
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wire eth_rx_ren;
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wire eth_tx_full;
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wire [63:0] eth_tx_data;
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wire eth_tx_eof;
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wire [2:0] eth_tx_occ;
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wire eth_tx_sof;
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wire eth_tx_valid;
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xge_mac xge_mac
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(
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// Outputs
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.pkt_rx_avail (eth_rx_avail),
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.pkt_rx_data (eth_rx_data),
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.pkt_rx_eop (eth_rx_eof),
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.pkt_rx_err (eth_rx_err),
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.pkt_rx_mod (eth_rx_occ),
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.pkt_rx_sop (eth_rx_sof),
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.pkt_rx_val (eth_rx_valid),
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.pkt_tx_full (eth_tx_full),
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.wb_ack_o (wb_ack_o),
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.wb_dat_o (wb_dat_o),
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.wb_int_o (xge_int),
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.xgmii_txc (xgmii_txc[7:0]),
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.xgmii_txd (xgmii_txd[63:0]),
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.mdc (mdc),
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.mdio_out (mdio_in),// Switch sense of in and out here for master and slave.
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.mdio_tri (mdio_tri),
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.xge_gpo ( ),
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// Inputs
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.clk_156m25 (xgmii_clk),
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.clk_xgmii_rx (xgmii_clk),
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.clk_xgmii_tx (xgmii_clk),
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.pkt_rx_ren (eth_rx_ren),
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.pkt_tx_data (eth_tx_data),
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.pkt_tx_eop (eth_tx_eof),
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.pkt_tx_mod (eth_tx_occ),
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.pkt_tx_sop (eth_tx_sof),
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.pkt_tx_val (eth_tx_valid),
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.reset_156m25_n (~xgmii_reset),
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.reset_xgmii_rx_n (~xgmii_reset),
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.reset_xgmii_tx_n (~xgmii_reset),
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.wb_adr_i (wb_adr_i[7:0]),
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.wb_clk_i (wb_clk_i),
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.wb_cyc_i (wb_cyc_i),
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.wb_dat_i (wb_dat_i),
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.wb_rst_i (wb_rst_i),
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.wb_stb_i (wb_stb_i),
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.wb_we_i (wb_we_i),
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.xgmii_rxc (xgmii_rxc[7:0]),
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.xgmii_rxd (xgmii_rxd[63:0]),
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.mdio_in (mdio_out), // Switch sense of in and out here for master and slave.
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.xge_gpi (/*{2'b00,align_status,mgt_tx_ready,sync_status[3:0]}*/0)
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);
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///////////////////////////////////////////////////////////////////////////////////////
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// RX FIFO Chain
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///////////////////////////////////////////////////////////////////////////////////////
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wire [63:0] rx_tdata_int;
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wire [3:0] rx_tuser_int;
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wire rx_tlast_int;
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wire rx_tvalid_int;
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wire rx_tready_int;
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//
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// Logic to drive pkt_rx_ren on XGE MAC
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//
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xge_handshake xge_handshake
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(
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.clk(xgmii_clk),
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.reset(xgmii_reset),
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.pkt_rx_ren(eth_rx_ren),
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.pkt_rx_avail(eth_rx_avail),
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.pkt_rx_eop(eth_rx_eof)
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);
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//
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// Add pad of 6 empty bytes before MAC addresses of new Rxed packet so that IP
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// headers are alligned. Also put metadata in first octet of pad that shows
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// ingress port.
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//
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xge64_to_axi64 #(.LABEL(PORTNUM)) xge64_to_axi64
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(
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.clk(xgmii_clk),
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.reset(xgmii_reset),
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.clear(clear),
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.datain(eth_rx_data),
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.occ(eth_rx_occ),
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.sof(eth_rx_sof),
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.eof(eth_rx_eof),
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.err(eth_rx_err),
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.valid(eth_rx_valid),
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.axis_tdata(rx_tdata_int),
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.axis_tuser(rx_tuser_int),
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.axis_tlast(rx_tlast_int),
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.axis_tvalid(rx_tvalid_int),
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.axis_tready(rx_tready_int)
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);
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//
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// Large FIFO must be able to run input side at 64b@156MHz to sustain 10Gb Rx.
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//
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axi64_4k_2clk_fifo rxfifo_2clk
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(
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.s_aresetn(~xgmii_reset),
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.s_aclk(xgmii_clk),
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.s_axis_tvalid(rx_tvalid_int),
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.s_axis_tready(rx_tready_int),
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.s_axis_tdata(rx_tdata_int),
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.s_axis_tlast(rx_tlast_int),
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.s_axis_tuser(rx_tuser_int),
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.axis_wr_data_count(),
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.m_aclk(sys_clk),
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.m_axis_tvalid(rx_tvalid),
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.m_axis_tready(rx_tready),
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.m_axis_tdata(rx_tdata),
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.m_axis_tlast(rx_tlast),
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.m_axis_tuser(rx_tuser),
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.axis_rd_data_count() );
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///////////////////////////////////////////////////////////////////////////////////////
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// TX FIFO Chain
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///////////////////////////////////////////////////////////////////////////////////////
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wire [63:0] tx_tdata_int;
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wire [3:0] tx_tuser_int;
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wire tx_tlast_int;
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wire tx_tvalid_int;
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wire tx_tready_int;
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wire [63:0] tx_tdata_int2;
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wire [3:0] tx_tuser_int2;
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wire tx_tlast_int2;
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wire tx_tvalid_int2;
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wire tx_tready_int2;
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wire tx_tvalid_int3;
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wire tx_tready_int3;
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wire tx_sof_int3;
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axi64_4k_2clk_fifo txfifo_2clk_1x
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(
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.s_aresetn(~xgmii_reset),
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.s_aclk(sys_clk),
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.s_axis_tvalid(tx_tvalid),
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.s_axis_tready(tx_tready),
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.s_axis_tdata(tx_tdata),
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.s_axis_tlast(tx_tlast),
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.s_axis_tuser(tx_tuser),
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.axis_wr_data_count(),
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.m_aclk(xgmii_clk),
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.m_axis_tvalid(tx_tvalid_int),
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.m_axis_tready(tx_tready_int),
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.m_axis_tdata(tx_tdata_int),
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.m_axis_tlast(tx_tlast_int),
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.m_axis_tuser(tx_tuser_int),
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.axis_rd_data_count() );
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//
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// Strip the 6 octet ethernet padding we used internally.
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// Put SOF into bit[3] of tuser.
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//
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axi64_to_xge64 axi64_to_xge64
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(
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.clk(xgmii_clk),
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.reset(xgmii_reset),
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.clear(clear),
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.s_axis_tdata(tx_tdata_int),
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.s_axis_tuser(tx_tuser_int),
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.s_axis_tlast(tx_tlast_int),
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.s_axis_tvalid(tx_tvalid_int),
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.s_axis_tready(tx_tready_int),
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.m_axis_tdata(tx_tdata_int2),
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.m_axis_tuser(tx_tuser_int2),
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.m_axis_tlast(tx_tlast_int2),
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.m_axis_tvalid(tx_tvalid_int2),
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.m_axis_tready(tx_tready_int2)
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);
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//
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// Large FIFO can hold a max sized ethernet packet.
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//
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axi64_8k_2clk_fifo txfifo_2clk_2
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(
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.s_aresetn(~xgmii_reset),
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.s_aclk(xgmii_clk),
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.s_axis_tvalid(tx_tvalid_int2),
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.s_axis_tready(tx_tready_int2),
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.s_axis_tdata(tx_tdata_int2),
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.s_axis_tlast(tx_tlast_int2),
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.s_axis_tuser(tx_tuser_int2),
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.axis_wr_data_count(),
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.m_aclk(xgmii_clk),
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.m_axis_tvalid(tx_tvalid_int3),
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.m_axis_tready(tx_tready_int3),
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.m_axis_tdata(eth_tx_data),
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.m_axis_tlast(eth_tx_eof),
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.m_axis_tuser({tx_sof_int3,eth_tx_occ}),
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.axis_rd_data_count() );
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//
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// Monitor number of Ethernet packets in tx_fifo2
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//
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axi_count_packets_in_fifo axi_count_packets_in_fifo
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(
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.clk(xgmii_clk),
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.reset(xgmii_reset),
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.in_axis_tvalid(tx_tvalid_int2),
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.in_axis_tready(tx_tready_int2),
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.in_axis_tlast(tx_tlast_int2),
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.out_axis_tvalid(tx_tvalid_int3),
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.out_axis_tready(tx_tready_int3),
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.out_axis_tlast(eth_tx_eof),
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.pkt_tx_full(eth_tx_full),
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.enable_tx(enable_tx) );
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//
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//
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// Supress FIFO flags to stop overflow of MAC in Tx direction
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//
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assign eth_tx_valid = tx_tvalid_int3 & enable_tx;
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assign tx_tready_int3 = enable_tx;
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assign eth_tx_sof = tx_sof_int3 & enable_tx;
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endmodule
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