61 lines
1009 B
Verilog
61 lines
1009 B
Verilog
//
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// Copyright 2013 Ettus Research LLC
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//
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//
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//
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// Provide required handshake to Opencores XGE MAC to initiate Rx of one available packet
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//
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//
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module xge_handshake
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(
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input clk,
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input reset,
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output reg pkt_rx_ren,
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input pkt_rx_avail,
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input pkt_rx_eop
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);
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localparam IDLE=0;
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localparam RX=1;
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reg state;
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always @(posedge clk)
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if (reset) begin
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pkt_rx_ren <= 0;
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state <= IDLE;
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end else begin
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case (state)
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//
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// Wait for pkt_rx_avail to be asserted, then assert pkt_rx_ren next cycle
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//
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IDLE: begin
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if (pkt_rx_avail) begin
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pkt_rx_ren <= 1;
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state <= RX;
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end else begin
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pkt_rx_ren <= 0;
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state <= IDLE;
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end
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end
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//
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// Keep pkt_rx_ren asserted until EOF received.
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//
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RX: begin
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if (pkt_rx_eop) begin
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pkt_rx_ren <= 0;
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state <= IDLE;
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end else begin
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pkt_rx_ren <= 1;
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state <= RX;
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end
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end
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endcase // case(state)
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end // else: !if(reset)
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endmodule // xge_handshake
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