939 lines
28 KiB
Verilog
939 lines
28 KiB
Verilog
//////////////////////////////////////////////////////////////////////
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//// ////
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//// File name "tx_dequeue.v" ////
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//// ////
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//// This file is part of the "10GE MAC" project ////
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//// http://www.opencores.org/cores/xge_mac/ ////
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//// ////
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//// Author(s): ////
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//// - A. Tanguay (antanguay@opencores.org) ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2008 AUTHORS. All rights reserved. ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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`include "defines.v"
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module tx_dequeue(/*AUTOARG*/
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// Outputs
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txdfifo_ren, txhfifo_ren, txhfifo_wdata, txhfifo_wstatus,
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txhfifo_wen, xgmii_txd, xgmii_txc, status_txdfifo_udflow_tog,
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// Inputs
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clk_xgmii_tx, reset_xgmii_tx_n, ctrl_tx_enable_ctx,
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status_local_fault_ctx, status_remote_fault_ctx, txdfifo_rdata,
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txdfifo_rstatus, txdfifo_rempty, txdfifo_ralmost_empty,
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txhfifo_rdata, txhfifo_rstatus, txhfifo_rempty,
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txhfifo_ralmost_empty, txhfifo_wfull, txhfifo_walmost_full
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);
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`include "CRC32_D64.v"
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`include "CRC32_D8.v"
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`include "utils.v"
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input clk_xgmii_tx;
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input reset_xgmii_tx_n;
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input ctrl_tx_enable_ctx;
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input status_local_fault_ctx;
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input status_remote_fault_ctx;
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input [63:0] txdfifo_rdata;
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input [7:0] txdfifo_rstatus;
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input txdfifo_rempty;
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input txdfifo_ralmost_empty;
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input [63:0] txhfifo_rdata;
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input [7:0] txhfifo_rstatus;
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input txhfifo_rempty;
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input txhfifo_ralmost_empty;
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input txhfifo_wfull;
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input txhfifo_walmost_full;
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output txdfifo_ren;
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output txhfifo_ren;
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output [63:0] txhfifo_wdata;
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output [7:0] txhfifo_wstatus;
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output txhfifo_wen;
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output [63:0] xgmii_txd;
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output [7:0] xgmii_txc;
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output status_txdfifo_udflow_tog;
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/*AUTOREG*/
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// Beginning of automatic regs (for this module's undeclared outputs)
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reg status_txdfifo_udflow_tog;
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reg txdfifo_ren;
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reg txhfifo_ren;
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reg [63:0] txhfifo_wdata;
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reg txhfifo_wen;
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reg [7:0] txhfifo_wstatus;
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reg [7:0] xgmii_txc;
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reg [63:0] xgmii_txd;
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// End of automatics
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/*AUTOWIRE*/
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reg [63:0] xgxs_txd;
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reg [7:0] xgxs_txc;
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reg [63:0] next_xgxs_txd;
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reg [7:0] next_xgxs_txc;
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reg [2:0] curr_state_enc;
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reg [2:0] next_state_enc;
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reg [0:0] curr_state_pad;
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reg [0:0] next_state_pad;
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reg start_on_lane0;
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reg next_start_on_lane0;
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reg [2:0] ifg_deficit;
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reg [2:0] next_ifg_deficit;
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reg ifg_4b_add;
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reg next_ifg_4b_add;
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reg ifg_8b_add;
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reg next_ifg_8b_add;
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reg ifg_8b2_add;
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reg next_ifg_8b2_add;
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reg [7:0] eop;
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reg [7:0] next_eop;
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reg [63:32] xgxs_txd_barrel;
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reg [7:4] xgxs_txc_barrel;
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reg [63:0] txhfifo_rdata_d1;
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reg [13:0] byte_cnt;
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reg [31:0] crc32_d64;
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reg [31:0] crc32_d8;
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reg [31:0] crc32_tx;
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reg [63:0] shift_crc_data;
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reg [3:0] shift_crc_eop;
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reg [3:0] shift_crc_cnt;
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reg [31:0] crc_data;
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reg frame_available;
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reg next_frame_available;
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reg [63:0] next_txhfifo_wdata;
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reg [7:0] next_txhfifo_wstatus;
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reg next_txhfifo_wen;
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reg txdfifo_ren_d1;
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parameter [2:0]
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SM_IDLE = 3'd0,
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SM_PREAMBLE = 3'd1,
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SM_TX = 3'd2,
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SM_EOP = 3'd3,
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SM_TERM = 3'd4,
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SM_TERM_FAIL = 3'd5,
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SM_IFG = 3'd6;
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parameter [0:0]
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SM_PAD_EQ = 1'd0,
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SM_PAD_PAD = 1'd1;
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//---
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// RC layer
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always @(posedge clk_xgmii_tx or negedge reset_xgmii_tx_n) begin
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if (reset_xgmii_tx_n == 1'b0) begin
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xgmii_txd <= {8{`IDLE}};
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xgmii_txc <= 8'hff;
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end
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else begin
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//---
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// RC Layer, insert local or remote fault messages based on status
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// of fault state-machine
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if (status_local_fault_ctx) begin
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// If local fault detected, send remote fault message to
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// link partner
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xgmii_txd <= {`REMOTE_FAULT, 8'h0, 8'h0, `SEQUENCE,
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`REMOTE_FAULT, 8'h0, 8'h0, `SEQUENCE};
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xgmii_txc <= {4'b0001, 4'b0001};
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end
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else if (status_remote_fault_ctx) begin
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// If remote fault detected, inhibit transmission and send
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// idle codes
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xgmii_txd <= {8{`IDLE}};
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xgmii_txc <= 8'hff;
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end
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else begin
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xgmii_txd <= xgxs_txd;
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xgmii_txc <= xgxs_txc;
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end
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end
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end
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always @(posedge clk_xgmii_tx or negedge reset_xgmii_tx_n) begin
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if (reset_xgmii_tx_n == 1'b0) begin
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curr_state_enc <= SM_IDLE;
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start_on_lane0 <= 1'b1;
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ifg_deficit <= 3'b0;
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ifg_4b_add <= 1'b0;
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ifg_8b_add <= 1'b0;
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ifg_8b2_add <= 1'b0;
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eop <= 8'b0;
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txhfifo_rdata_d1 <= 64'b0;
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xgxs_txd_barrel <= {4{`IDLE}};
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xgxs_txc_barrel <= 4'hf;
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frame_available <= 1'b0;
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xgxs_txd <= {8{`IDLE}};
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xgxs_txc <= 8'hff;
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status_txdfifo_udflow_tog <= 1'b0;
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end
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else begin
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curr_state_enc <= next_state_enc;
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start_on_lane0 <= next_start_on_lane0;
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ifg_deficit <= next_ifg_deficit;
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ifg_4b_add <= next_ifg_4b_add;
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ifg_8b_add <= next_ifg_8b_add;
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ifg_8b2_add <= next_ifg_8b2_add;
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eop <= next_eop;
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txhfifo_rdata_d1 <= txhfifo_rdata;
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xgxs_txd_barrel <= next_xgxs_txd[63:32];
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xgxs_txc_barrel <= next_xgxs_txc[7:4];
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frame_available <= next_frame_available;
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//---
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// Barrel shifter. Previous stage always align packet with LANE0.
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// This stage allow us to shift packet to align with LANE4 if needed
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// for correct inter frame gap (IFG).
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if (next_start_on_lane0) begin
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xgxs_txd <= next_xgxs_txd;
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xgxs_txc <= next_xgxs_txc;
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end
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else begin
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xgxs_txd <= {next_xgxs_txd[31:0], xgxs_txd_barrel};
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xgxs_txc <= {next_xgxs_txc[3:0], xgxs_txc_barrel};
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end
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//---
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// FIFO errors, used to generate interrupts.
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if (txdfifo_ren && txdfifo_rempty) begin
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status_txdfifo_udflow_tog <= ~status_txdfifo_udflow_tog;
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end
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end
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end
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always @(/*AS*/crc32_tx or ctrl_tx_enable_ctx or curr_state_enc or eop
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or frame_available or ifg_4b_add or ifg_8b2_add or ifg_8b_add
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or ifg_deficit or start_on_lane0 or status_local_fault_ctx
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or txhfifo_ralmost_empty or txhfifo_rdata_d1
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or txhfifo_rempty or txhfifo_rstatus) begin
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next_state_enc = curr_state_enc;
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next_start_on_lane0 = start_on_lane0;
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next_ifg_deficit = ifg_deficit;
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next_ifg_4b_add = ifg_4b_add;
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next_ifg_8b_add = ifg_8b_add;
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next_ifg_8b2_add = ifg_8b2_add;
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next_eop = eop;
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next_xgxs_txd = {8{`IDLE}};
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next_xgxs_txc = 8'hff;
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txhfifo_ren = 1'b0;
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next_frame_available = frame_available;
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case (curr_state_enc)
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SM_IDLE:
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begin
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// Wait for frame to be available. There should be a least N bytes in the
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// data fifo or a crc in the control fifo. The N bytes in the data fifo
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// give time to the enqueue engine to calculate crc and write it to the
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// control fifo. If crc is already in control fifo we can start transmitting
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// with no concern. Transmission is inhibited if local or remote faults
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// are detected.
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if (ctrl_tx_enable_ctx && frame_available &&
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!status_local_fault_ctx && !status_local_fault_ctx) begin
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txhfifo_ren = 1'b1;
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next_state_enc = SM_PREAMBLE;
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end
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else begin
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next_frame_available = !txhfifo_ralmost_empty;
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next_ifg_4b_add = 1'b0;
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end
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end
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SM_PREAMBLE:
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begin
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// On reading SOP from fifo, send SFD and preamble characters
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if (txhfifo_rstatus[`TXSTATUS_SOP]) begin
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next_xgxs_txd = {`SFD, {6{`PREAMBLE}}, `START};
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next_xgxs_txc = 8'h01;
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txhfifo_ren = 1'b1;
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next_state_enc = SM_TX;
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end
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else begin
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next_frame_available = 1'b0;
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next_state_enc = SM_IDLE;
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end
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// Depending on deficit idle count calculations, add 4 bytes
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// or IFG or not. This will determine on which lane start the
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// next frame.
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if (ifg_4b_add) begin
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next_start_on_lane0 = 1'b0;
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end
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else begin
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next_start_on_lane0 = 1'b1;
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end
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end
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SM_TX:
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begin
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next_xgxs_txd = txhfifo_rdata_d1;
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next_xgxs_txc = 8'h00;
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txhfifo_ren = 1'b1;
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// Wait for EOP indication to be read from the fifo, then
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// transition to next state.
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if (txhfifo_rstatus[`TXSTATUS_EOP]) begin
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txhfifo_ren = 1'b0;
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next_frame_available = !txhfifo_ralmost_empty;
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next_state_enc = SM_EOP;
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end
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else if (txhfifo_rempty || txhfifo_rstatus[`TXSTATUS_SOP]) begin
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// Failure condition, we did not see EOP and there
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// is no more data in fifo or SOP, force end of packet transmit.
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next_state_enc = SM_TERM_FAIL;
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end
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next_eop[0] = txhfifo_rstatus[2:0] == 3'd1;
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next_eop[1] = txhfifo_rstatus[2:0] == 3'd2;
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next_eop[2] = txhfifo_rstatus[2:0] == 3'd3;
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next_eop[3] = txhfifo_rstatus[2:0] == 3'd4;
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next_eop[4] = txhfifo_rstatus[2:0] == 3'd5;
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next_eop[5] = txhfifo_rstatus[2:0] == 3'd6;
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next_eop[6] = txhfifo_rstatus[2:0] == 3'd7;
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next_eop[7] = txhfifo_rstatus[2:0] == 3'd0;
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end
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SM_EOP:
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begin
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// Insert TERMINATE character in correct lane depending on position
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// of EOP read from fifo. Also insert CRC read from control fifo.
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if (eop[0]) begin
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next_xgxs_txd = {{2{`IDLE}}, `TERMINATE,
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crc32_tx[31:0], txhfifo_rdata_d1[7:0]};
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next_xgxs_txc = 8'b11100000;
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end
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if (eop[1]) begin
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next_xgxs_txd = {`IDLE, `TERMINATE,
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crc32_tx[31:0], txhfifo_rdata_d1[15:0]};
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next_xgxs_txc = 8'b11000000;
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end
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if (eop[2]) begin
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next_xgxs_txd = {`TERMINATE, crc32_tx[31:0], txhfifo_rdata_d1[23:0]};
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next_xgxs_txc = 8'b10000000;
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end
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if (eop[3]) begin
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next_xgxs_txd = {crc32_tx[31:0], txhfifo_rdata_d1[31:0]};
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next_xgxs_txc = 8'b00000000;
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end
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if (eop[4]) begin
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next_xgxs_txd = {crc32_tx[23:0], txhfifo_rdata_d1[39:0]};
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next_xgxs_txc = 8'b00000000;
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end
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if (eop[5]) begin
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next_xgxs_txd = {crc32_tx[15:0], txhfifo_rdata_d1[47:0]};
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next_xgxs_txc = 8'b00000000;
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end
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if (eop[6]) begin
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next_xgxs_txd = {crc32_tx[7:0], txhfifo_rdata_d1[55:0]};
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next_xgxs_txc = 8'b00000000;
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end
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if (eop[7]) begin
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next_xgxs_txd = {txhfifo_rdata_d1[63:0]};
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next_xgxs_txc = 8'b00000000;
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end
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if (!frame_available) begin
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// If there is not another frame ready to be transmitted, interface
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// will go idle and idle deficit idle count calculation is irrelevant.
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// Set deficit to 0.
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next_ifg_deficit = 3'b0;
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end
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else begin
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// Idle deficit count calculated based on number of "wasted" bytes
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// between TERMINATE and alignment of next frame in LANE0.
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next_ifg_deficit = ifg_deficit +
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{2'b0, eop[0] | eop[4]} +
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{1'b0, eop[1] | eop[5], 1'b0} +
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{1'b0, eop[2] | eop[6],
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eop[2] | eop[6]};
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end
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// IFG corrections based on deficit count and previous starting lane
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|
// Calculated based on following table:
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//
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// DIC=0 DIC=1 DIC=2 DIC=3
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// ------------- ------------- ------------- -------------
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// PktLen IFG Next IFG Next IFG Next IFG Next
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// Modulus Length DIC Length DIC Length DIC Length DIC
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// -----------------------------------------------------------------------
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// 0 12 0 12 1 12 2 12 3
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// 1 11 1 11 2 11 3 15 0
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// 2 10 2 10 3 14 0 14 1
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// 3 9 3 13 0 13 1 13 2
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//
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//
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// In logic it translates into adding 4, 8, or 12 bytes of IFG relative
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// to LANE0.
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// IFG and Add columns assume no deficit applied
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// IFG+DIC and Add+DIC assume deficit must be applied
|
|
//
|
|
// Start lane 0 Start lane 4
|
|
// EOP Pads IFG IFG+DIC Add Add+DIC Add Add IFG
|
|
// 0 3 11 15 8 12 12 16
|
|
// 1 2 10 14 8 12 12 16
|
|
// 2 1 9 13 8 12 12 16
|
|
// 3 8 12 12 4 4 8 8
|
|
// 4 7 11 15 4 8 8 12
|
|
// 5 6 10 14 4 8 8 12
|
|
// 6 5 9 13 4 8 8 12
|
|
// 7 4 12 12 8 8 12 12
|
|
|
|
if (!frame_available) begin
|
|
|
|
// If there is not another frame ready to be transmitted, interface
|
|
// will go idle and idle deficit idle count calculation is irrelevant.
|
|
|
|
next_ifg_4b_add = 1'b0;
|
|
next_ifg_8b_add = 1'b0;
|
|
next_ifg_8b2_add = 1'b0;
|
|
|
|
end
|
|
else if (next_ifg_deficit[2] == ifg_deficit[2]) begin
|
|
|
|
// Add 4 bytes IFG
|
|
|
|
next_ifg_4b_add = (eop[0] & !start_on_lane0) |
|
|
(eop[1] & !start_on_lane0) |
|
|
(eop[2] & !start_on_lane0) |
|
|
(eop[3] & start_on_lane0) |
|
|
(eop[4] & start_on_lane0) |
|
|
(eop[5] & start_on_lane0) |
|
|
(eop[6] & start_on_lane0) |
|
|
(eop[7] & !start_on_lane0);
|
|
|
|
// Add 8 bytes IFG
|
|
|
|
next_ifg_8b_add = (eop[0]) |
|
|
(eop[1]) |
|
|
(eop[2]) |
|
|
(eop[3] & !start_on_lane0) |
|
|
(eop[4] & !start_on_lane0) |
|
|
(eop[5] & !start_on_lane0) |
|
|
(eop[6] & !start_on_lane0) |
|
|
(eop[7]);
|
|
|
|
// Add another 8 bytes IFG
|
|
|
|
next_ifg_8b2_add = 1'b0;
|
|
|
|
end
|
|
else begin
|
|
|
|
// Add 4 bytes IFG
|
|
|
|
next_ifg_4b_add = (eop[0] & start_on_lane0) |
|
|
(eop[1] & start_on_lane0) |
|
|
(eop[2] & start_on_lane0) |
|
|
(eop[3] & start_on_lane0) |
|
|
(eop[4] & !start_on_lane0) |
|
|
(eop[5] & !start_on_lane0) |
|
|
(eop[6] & !start_on_lane0) |
|
|
(eop[7] & !start_on_lane0);
|
|
|
|
// Add 8 bytes IFG
|
|
|
|
next_ifg_8b_add = (eop[0]) |
|
|
(eop[1]) |
|
|
(eop[2]) |
|
|
(eop[3] & !start_on_lane0) |
|
|
(eop[4]) |
|
|
(eop[5]) |
|
|
(eop[6]) |
|
|
(eop[7]);
|
|
|
|
// Add another 8 bytes IFG
|
|
|
|
next_ifg_8b2_add = (eop[0] & !start_on_lane0) |
|
|
(eop[1] & !start_on_lane0) |
|
|
(eop[2] & !start_on_lane0);
|
|
|
|
end
|
|
|
|
if (|eop[2:0]) begin
|
|
|
|
if (frame_available) begin
|
|
|
|
// Next state depends on number of IFG bytes to be inserted.
|
|
// Skip idle state if needed.
|
|
|
|
if (next_ifg_8b2_add) begin
|
|
next_state_enc = SM_IFG;
|
|
end
|
|
else if (next_ifg_8b_add) begin
|
|
next_state_enc = SM_IDLE;
|
|
end
|
|
else begin
|
|
txhfifo_ren = 1'b1;
|
|
next_state_enc = SM_PREAMBLE;
|
|
end
|
|
|
|
end
|
|
else begin
|
|
next_state_enc = SM_IFG;
|
|
end
|
|
end
|
|
|
|
if (|eop[7:3]) begin
|
|
next_state_enc = SM_TERM;
|
|
end
|
|
|
|
end
|
|
|
|
SM_TERM:
|
|
begin
|
|
|
|
// Insert TERMINATE character in correct lane depending on position
|
|
// of EOP read from fifo. Also insert CRC read from control fifo.
|
|
|
|
if (eop[3]) begin
|
|
next_xgxs_txd = {{7{`IDLE}}, `TERMINATE};
|
|
next_xgxs_txc = 8'b11111111;
|
|
end
|
|
|
|
if (eop[4]) begin
|
|
next_xgxs_txd = {{6{`IDLE}}, `TERMINATE, crc32_tx[31:24]};
|
|
next_xgxs_txc = 8'b11111110;
|
|
end
|
|
|
|
if (eop[5]) begin
|
|
next_xgxs_txd = {{5{`IDLE}}, `TERMINATE, crc32_tx[31:16]};
|
|
next_xgxs_txc = 8'b11111100;
|
|
end
|
|
|
|
if (eop[6]) begin
|
|
next_xgxs_txd = {{4{`IDLE}}, `TERMINATE, crc32_tx[31:8]};
|
|
next_xgxs_txc = 8'b11111000;
|
|
end
|
|
|
|
if (eop[7]) begin
|
|
next_xgxs_txd = {{3{`IDLE}}, `TERMINATE, crc32_tx[31:0]};
|
|
next_xgxs_txc = 8'b11110000;
|
|
end
|
|
|
|
// Next state depends on number of IFG bytes to be inserted.
|
|
// Skip idle state if needed.
|
|
|
|
if (frame_available && !ifg_8b_add) begin
|
|
txhfifo_ren = 1'b1;
|
|
next_state_enc = SM_PREAMBLE;
|
|
end
|
|
else if (frame_available) begin
|
|
next_state_enc = SM_IDLE;
|
|
end
|
|
else begin
|
|
next_state_enc = SM_IFG;
|
|
end
|
|
|
|
end
|
|
|
|
SM_TERM_FAIL:
|
|
begin
|
|
|
|
next_xgxs_txd = {{7{`IDLE}}, `TERMINATE};
|
|
next_xgxs_txc = 8'b11111111;
|
|
next_state_enc = SM_IFG;
|
|
|
|
end
|
|
|
|
SM_IFG:
|
|
begin
|
|
|
|
next_state_enc = SM_IDLE;
|
|
|
|
end
|
|
|
|
default:
|
|
begin
|
|
next_state_enc = SM_IDLE;
|
|
end
|
|
|
|
endcase
|
|
|
|
end
|
|
|
|
|
|
always @(/*AS*/crc32_d64 or txhfifo_wen or txhfifo_wstatus) begin
|
|
|
|
if (txhfifo_wen && txhfifo_wstatus[`TXSTATUS_SOP]) begin
|
|
crc_data = 32'hffffffff;
|
|
end
|
|
else begin
|
|
crc_data = crc32_d64;
|
|
end
|
|
|
|
end
|
|
|
|
always @(/*AS*/byte_cnt or curr_state_pad or txdfifo_rdata
|
|
or txdfifo_rempty or txdfifo_ren_d1 or txdfifo_rstatus
|
|
or txhfifo_walmost_full) begin
|
|
|
|
next_state_pad = curr_state_pad;
|
|
|
|
next_txhfifo_wdata = txdfifo_rdata;
|
|
next_txhfifo_wstatus = txdfifo_rstatus;
|
|
|
|
txdfifo_ren = 1'b0;
|
|
next_txhfifo_wen = 1'b0;
|
|
|
|
case (curr_state_pad)
|
|
|
|
SM_PAD_EQ: begin
|
|
|
|
|
|
//---
|
|
// If room availabe in hoding fifo and data available in
|
|
// data fifo, transfer data words. If transmit state machine
|
|
// is reading from fifo we can assume room will be available.
|
|
|
|
if (!txhfifo_walmost_full) begin
|
|
|
|
txdfifo_ren = !txdfifo_rempty;
|
|
|
|
end
|
|
|
|
|
|
//---
|
|
// This logic dependent on read during previous cycle.
|
|
|
|
if (txdfifo_ren_d1) begin
|
|
|
|
next_txhfifo_wen = 1'b1;
|
|
|
|
// On EOP, decide if padding is required for this packet.
|
|
|
|
if (txdfifo_rstatus[`TXSTATUS_EOP]) begin
|
|
|
|
if (byte_cnt < 14'd56) begin
|
|
|
|
next_txhfifo_wstatus = `TXSTATUS_NONE;
|
|
txdfifo_ren = 1'b0;
|
|
next_state_pad = SM_PAD_PAD;
|
|
|
|
end
|
|
else if (byte_cnt == 14'd56 &&
|
|
(txdfifo_rstatus[2:0] == 3'd1 ||
|
|
txdfifo_rstatus[2:0] == 3'd2 ||
|
|
txdfifo_rstatus[2:0] == 3'd3)) begin
|
|
|
|
// Pad up to LANE3, keep the other 4 bytes for crc that will
|
|
// be inserted by dequeue engine.
|
|
|
|
next_txhfifo_wstatus[2:0] = 3'd4;
|
|
|
|
// Pad end bytes with zeros.
|
|
|
|
if (txdfifo_rstatus[2:0] == 3'd1)
|
|
next_txhfifo_wdata[31:8] = 24'b0;
|
|
if (txdfifo_rstatus[2:0] == 3'd2)
|
|
next_txhfifo_wdata[31:16] = 16'b0;
|
|
if (txdfifo_rstatus[2:0] == 3'd3)
|
|
next_txhfifo_wdata[31:24] = 8'b0;
|
|
|
|
txdfifo_ren = 1'b0;
|
|
|
|
end
|
|
else begin
|
|
|
|
txdfifo_ren = 1'b0;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
end
|
|
|
|
end
|
|
|
|
SM_PAD_PAD: begin
|
|
|
|
//---
|
|
// Pad packet to 64 bytes by writting zeros to holding fifo.
|
|
|
|
if (!txhfifo_walmost_full) begin
|
|
|
|
next_txhfifo_wdata = 64'b0;
|
|
next_txhfifo_wstatus = `TXSTATUS_NONE;
|
|
next_txhfifo_wen = 1'b1;
|
|
|
|
if (byte_cnt == 14'd56) begin
|
|
|
|
|
|
// Pad up to LANE3, keep the other 4 bytes for crc that will
|
|
// be inserted by dequeue engine.
|
|
|
|
next_txhfifo_wstatus[`TXSTATUS_EOP] = 1'b1;
|
|
next_txhfifo_wstatus[2:0] = 3'd4;
|
|
|
|
next_state_pad = SM_PAD_EQ;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
end
|
|
|
|
default:
|
|
begin
|
|
next_state_pad = SM_PAD_EQ;
|
|
end
|
|
|
|
endcase
|
|
|
|
end
|
|
|
|
|
|
always @(posedge clk_xgmii_tx or negedge reset_xgmii_tx_n) begin
|
|
|
|
if (reset_xgmii_tx_n == 1'b0) begin
|
|
|
|
curr_state_pad <= SM_PAD_EQ;
|
|
|
|
txdfifo_ren_d1 <= 1'b0;
|
|
|
|
txhfifo_wdata <= 64'b0;
|
|
txhfifo_wstatus <= 8'b0;
|
|
txhfifo_wen <= 1'b0;
|
|
|
|
byte_cnt <= 14'b0;
|
|
|
|
shift_crc_data <= 64'b0;
|
|
shift_crc_eop <= 4'b0;
|
|
shift_crc_cnt <= 4'b0;
|
|
|
|
end
|
|
else begin
|
|
|
|
curr_state_pad <= next_state_pad;
|
|
|
|
txdfifo_ren_d1 <= txdfifo_ren;
|
|
|
|
txhfifo_wdata <= next_txhfifo_wdata;
|
|
txhfifo_wstatus <= next_txhfifo_wstatus;
|
|
txhfifo_wen <= next_txhfifo_wen;
|
|
|
|
|
|
//---
|
|
// Reset byte count on SOP
|
|
|
|
if (next_txhfifo_wen) begin
|
|
|
|
if (next_txhfifo_wstatus[`TXSTATUS_SOP]) begin
|
|
|
|
byte_cnt <= 14'd8;
|
|
|
|
end
|
|
else begin
|
|
|
|
byte_cnt <= byte_cnt + 14'd8;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
|
|
//---
|
|
// Calculate CRC as data is written to holding fifo. The holding fifo creates
|
|
// a delay that allow the CRC calculation to complete before the end of the frame
|
|
// is ready to be transmited.
|
|
|
|
if (txhfifo_wen) begin
|
|
|
|
crc32_d64 <= nextCRC32_D64(reverse_64b(txhfifo_wdata), crc_data);
|
|
|
|
end
|
|
|
|
if (txhfifo_wen && txhfifo_wstatus[`TXSTATUS_EOP]) begin
|
|
|
|
// Last bytes calculated 8-bit at a time instead of 64-bit. Start
|
|
// this process at the end of the frame.
|
|
|
|
crc32_d8 <= crc32_d64;
|
|
|
|
shift_crc_data <= txhfifo_wdata;
|
|
shift_crc_cnt <= 4'd9;
|
|
|
|
if (txhfifo_wstatus[2:0] == 3'b0) begin
|
|
shift_crc_eop <= 4'd8;
|
|
end
|
|
else begin
|
|
shift_crc_eop <= {1'b0, txhfifo_wstatus[2:0]};
|
|
end
|
|
|
|
end
|
|
else if (shift_crc_eop != 4'b0) begin
|
|
|
|
// Complete crc calculation 8-bit at a time until finished. This can
|
|
// be 1 to 8 bytes long.
|
|
|
|
crc32_d8 <= nextCRC32_D8(reverse_8b(shift_crc_data[7:0]), crc32_d8);
|
|
|
|
shift_crc_data <= {8'b0, shift_crc_data[63:8]};
|
|
shift_crc_eop <= shift_crc_eop - 4'd1;
|
|
|
|
end
|
|
|
|
|
|
//---
|
|
// Update CRC register at the end of calculation. Always update after 8
|
|
// cycles for deterministic results, even if a single byte was present in
|
|
// last data word.
|
|
|
|
if (shift_crc_cnt == 4'b1) begin
|
|
|
|
crc32_tx <= ~reverse_32b(crc32_d8);
|
|
|
|
end
|
|
else begin
|
|
|
|
shift_crc_cnt <= shift_crc_cnt - 4'd1;
|
|
|
|
end
|
|
|
|
end
|
|
|
|
end
|
|
|
|
endmodule
|
|
|