Ashish Chaudhari
adf2da6ac7
- Fixed 10GigE firmware communication issues and sequence errors for TX - Multiple changes to help ease timing closure - Cleaned up build scripts - Switched to Xilinx ISE 14.7 as the default build tool for X300 Original-commit: 64d71dcbc5fa6790385b288de25224d386b047b0
72 lines
1.5 KiB
Verilog
72 lines
1.5 KiB
Verilog
//
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// Copyright 2014 Ettus Research LLC
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//
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module axis_packet_debug (
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input clk,
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input reset,
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input clear,
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//Packet In
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input [63:0] tdata,
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input tlast,
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input tvalid,
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input tready,
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//Per packet info
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output reg pkt_strobe,
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output reg [15:0] length,
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output reg [63:0] checksum,
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//Statistics
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output reg [31:0] pkt_count
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);
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localparam ST_HEADER = 1'b0;
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localparam ST_DATA = 1'b1;
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//Packet state logic
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reg pkt_state;
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always @(posedge clk) begin
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if (reset) begin
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pkt_state <= ST_HEADER;
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end else if (tvalid & tready) begin
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pkt_state <= tlast ? ST_HEADER : ST_DATA;
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end
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end
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//Trigger logic
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always @(posedge clk)
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if (reset)
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pkt_strobe <= 1'b0;
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else
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pkt_strobe <= tvalid & tready & tlast;
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//Length capture
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always @(posedge clk)
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if (reset || pkt_state == ST_HEADER)
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length <= tlast ? 16'd8 : 16'd0;
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else
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if (tvalid & tready)
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length <= length + 16'd8;
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//Checksum capture
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always @(posedge clk)
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if (reset || pkt_state == ST_HEADER)
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checksum <= 64'd0;
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else
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if (tvalid & tready)
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checksum <= checksum ^ tdata;
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//Counts
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always @(posedge clk)
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if (reset | clear) begin
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pkt_count <= 32'd0;
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end else begin
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if (tvalid & tready & tlast) begin
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pkt_count <= pkt_count + 32'd1;
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end
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end
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endmodule // cvita_packet_debug
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