adf6f576c6
FPGA: - Split up MB registers that control daughterboard specific settings so that daughterboards 0 and 1 could have different setings, in preparation for future devices that require different settings. This requires a compat number bump to 8.0. - Add registers for additional RFDC information, including the block/tile mapping of the individual channels, and information about resampling capabilities - Identify sections of code that would be specific to X410/ZBX and move them to their own headers, so it's trivial to add device-specific sections of code instead for other devices in the future. - This includes constraints for clocks and I/O pins. - Remove ability to do timed ctrlport transactions to the MB CPLD, this was unused and possibly broken. - Move daughterboard-specific code into its own code location (dboards/zbx) - Move X410-specific register documentation to its own location (doc/X410) - Refactor Makefiles to split out X410/ZBX specific components and allow switching between device types - Add 512-bit AXI interconnects - Make number of timekeepers configurable (X410 keeps the single timekeeper) MPM: - Required compat is bumped to 8.0 - Now supports new registers for detecting DSP capabilities and multi-rate settings for the daughterboards - Adds MMCM controls (currently unused) Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
60 lines
2.9 KiB
Tcl
60 lines
2.9 KiB
Tcl
#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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# Description:
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# DB GPIO pin constraints for X410.
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#
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###############################################################################
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# Pin constraints for the other PL pins (1.8 V)
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###############################################################################
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set_property PACKAGE_PIN F6 [get_ports {DB1_GPIO[0]}]
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set_property PACKAGE_PIN E6 [get_ports {DB1_GPIO[1]}]
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set_property PACKAGE_PIN E9 [get_ports {DB1_GPIO[2]}]
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set_property PACKAGE_PIN E8 [get_ports {DB1_GPIO[3]}]
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set_property PACKAGE_PIN E7 [get_ports {DB1_GPIO[4]}]
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set_property PACKAGE_PIN D6 [get_ports {DB1_GPIO[5]}]
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set_property PACKAGE_PIN D10 [get_ports {DB1_GPIO[6]}]
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set_property PACKAGE_PIN C10 [get_ports {DB1_GPIO[7]}]
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set_property PACKAGE_PIN C8 [get_ports {DB1_GPIO[8]}]
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set_property PACKAGE_PIN C7 [get_ports {DB1_GPIO[9]}]
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set_property PACKAGE_PIN D9 [get_ports {DB1_GPIO[10]}]
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set_property PACKAGE_PIN D8 [get_ports {DB1_GPIO[11]}]
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set_property PACKAGE_PIN B8 [get_ports {DB1_GPIO[12]}]
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set_property PACKAGE_PIN B7 [get_ports {DB1_GPIO[13]}]
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set_property PACKAGE_PIN B10 [get_ports {DB1_GPIO[14]}]
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set_property PACKAGE_PIN B9 [get_ports {DB1_GPIO[15]}]
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set_property PACKAGE_PIN C6 [get_ports {DB1_GPIO[16]}]
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set_property PACKAGE_PIN C5 [get_ports {DB1_GPIO[17]}]
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set_property PACKAGE_PIN B5 [get_ports {DB1_GPIO[18]}]
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set_property PACKAGE_PIN A5 [get_ports {DB1_GPIO[19]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB1_GPIO[*]}]
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set_property PULLDOWN TRUE [get_ports {DB1_GPIO[*]}]
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set_property IOB TRUE [get_ports {DB1_GPIO[*]}]
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set_property PACKAGE_PIN AW6 [get_ports {DB0_GPIO[0]}]
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set_property PACKAGE_PIN AW5 [get_ports {DB0_GPIO[1]}]
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set_property PACKAGE_PIN AW4 [get_ports {DB0_GPIO[2]}]
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set_property PACKAGE_PIN AW3 [get_ports {DB0_GPIO[3]}]
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set_property PACKAGE_PIN AV3 [get_ports {DB0_GPIO[4]}]
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set_property PACKAGE_PIN AV2 [get_ports {DB0_GPIO[5]}]
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set_property PACKAGE_PIN AU2 [get_ports {DB0_GPIO[6]}]
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set_property PACKAGE_PIN AU1 [get_ports {DB0_GPIO[7]}]
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set_property PACKAGE_PIN AV6 [get_ports {DB0_GPIO[8]}]
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set_property PACKAGE_PIN AV5 [get_ports {DB0_GPIO[9]}]
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set_property PACKAGE_PIN AU4 [get_ports {DB0_GPIO[10]}]
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set_property PACKAGE_PIN AU3 [get_ports {DB0_GPIO[11]}]
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set_property PACKAGE_PIN AT5 [get_ports {DB0_GPIO[12]}]
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set_property PACKAGE_PIN AU5 [get_ports {DB0_GPIO[13]}]
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set_property PACKAGE_PIN AT7 [get_ports {DB0_GPIO[14]}]
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set_property PACKAGE_PIN AT6 [get_ports {DB0_GPIO[15]}]
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set_property PACKAGE_PIN AU8 [get_ports {DB0_GPIO[16]}]
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set_property PACKAGE_PIN AV8 [get_ports {DB0_GPIO[17]}]
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set_property PACKAGE_PIN AU7 [get_ports {DB0_GPIO[18]}]
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set_property PACKAGE_PIN AV7 [get_ports {DB0_GPIO[19]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {DB0_GPIO[*]}]
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set_property PULLDOWN TRUE [get_ports {DB0_GPIO[*]}]
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set_property IOB TRUE [get_ports {DB0_GPIO[*]}]
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