Joerg Hofrichter
e01ce08634
... to support custom image core name, example:
rfnoc_image_builder -y n310_rfnoc_image_core.yml -n my_custom_name
The device tree source files were renamed to match the target
name used in the Makefile.
example:
old: dts/usrp_n310_fpga_hg.dts
new: dts/N310_HG.dts
The source file is used to compile the final .dts file in the BUILD_DIR.
example: build-my_custom_name/N310_HG.dts
The final .dts file is copied to the BUILD_OUTPUT_DIR as part of the
post build steps and renamed to the custom image core name.
example: build/my_custom_name.dts
This completes the change that was introduced with commit 2afc66f132.
Original-commit: d40db57f2e03c322ac6b0001e0a59d4a14a5a3b9
158 lines
6.1 KiB
Makefile
158 lines
6.1 KiB
Makefile
#
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# Copyright 2018 Ettus Research LLC
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#
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# NOTE: All comments prefixed with a "##" will be displayed as a part of the "make help" target
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##-------------------
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##USRP E31X FPGA Help
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##-------------------
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##Usage:
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## rfnoc_image_builder -y <image core file> -t <target> -n <image core name>
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##
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## NOTE: For building E3x0 bitfiles, do not run make directly! Instead, use
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## rfnoc_image_builder. It will create all intermediate files, set up a Vivado
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## environment, and run Vivado to build a bitfile.
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##
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## There exist some special make targets which can be called directly like this:
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##
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## make <Targets> <Options>
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##
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##Output:
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## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header
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## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.dts: Device tree source file
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## $(BUILD_OUTPUT_DIR)/usrp_<product>_fpga_<image_type>.rpt: Build report (includes utilization and timing summary)
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# Base output directory for all builds.
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BUILD_BASE_DIR ?= .
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# Base directory for the build outputs.
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BUILD_OUTPUT_DIR ?= $(BUILD_BASE_DIR)/build
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# Initialize a build seed. This can be changed to randomly affect build results.
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BUILD_SEED ?= 0
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DEFS += BUILD_SEED=$(BUILD_SEED)
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# Set build option (check RTL, run synthesis, or do a full build)
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ifndef TARGET
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ifeq ($(CHECK), 1)
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TARGET = rtl
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else ifeq ($(SYNTH), 1)
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TARGET = synth
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else ifeq ($(IP_ONLY), 1)
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TARGET = viv_ip
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else
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TARGET = bin
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endif
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endif
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TOP ?= e31x
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# vivado_build($1=Device, $2=Definitions)
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vivado_build = make -f Makefile.e31x.inc $(TARGET) NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
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vivado_ip = make -f Makefile.e31x.inc viv_ip NAME=$@ ARCH=$(XIL_ARCH_$1) PART_ID=$(XIL_PART_ID_$1) $2 TOP_MODULE=$(TOP) EXTRA_DEFS="$2"
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# post_build($1=Device)
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ifeq ($(TARGET),bin)
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post_build = @\
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mkdir -p $(BUILD_OUTPUT_DIR); \
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echo "Exporting bitstream file..."; \
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cp $(BUILD_DIR)/e31x.bit $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).bit; \
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echo "Exporting build report..."; \
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cp $(BUILD_DIR)/build.rpt $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).rpt; \
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echo "Exporting devicetree file..."; \
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cp $(BUILD_DIR)/$(1).dts $(BUILD_OUTPUT_DIR)/$(IMAGE_CORE_NAME).dts; \
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echo "Build DONE ... $(1)";
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else
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post_build = @echo "Skipping bitfile export."
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endif
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##
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##Supported Targets
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##-----------------
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##Reminder: Targets are built by calling
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##
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## $ rfnoc_image_builder -y <image core file.yml> -t <target name> -n <image core name>
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##
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##The following table lists all valid combinations:
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##
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##--------------------------|---------------|-------------------------|------------------
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## Default Image core file | Target | Image core name | Description
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##--------------------------|---------------|-------------------------|------------------
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##e310_rfnoc_image_core.yml | E310_SG1 | usrp_e310_sg1_fpga | E310 speedgrade 1
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##e310_rfnoc_image_core.yml | E310_SG1_IDLE | usrp_e310_sg1_idle_fpga | E310 speedgrade 1, idle image
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##e310_rfnoc_image_core.yml | E310_SG3 | usrp_e310_sg3_fpga | E310 speedgrade 3
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##e310_rfnoc_image_core.yml | E310_SG3_IDLE | usrp_e310_sg3_idle_fpga | E310 speedgrade 3, idle image
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##
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##Of course, a custom YAML file may be used.
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##
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check-variables:
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ifndef IMAGE_CORE_NAME
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$(error IMAGE_CORE_NAME is not set! Use rfnoc_image_builder to create valid make commands)
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endif
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ifndef BUILD_DIR
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$(error BUILD_DIR is not set! Use rfnoc_image_builder to create valid make commands)
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endif
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##E310_SG1_IDLE: Build USRP E3XX idle design (Speed Grade 1).
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E310_SG1_IDLE E3XX_idle: check-variables E310_SG1_IP $(BUILD_DIR)/E310_SG1_IDLE.dts
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$(call vivado_build,E310_SG1,$(DEFS) E310_IDLE_IMAGE=1 E310_SG1=1)
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$(call post_build,E310_SG1_IDLE)
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##E310_SG3_IDLE: Build USRP E3XX idle design (Speed Grade 3).
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E310_SG3_IDLE E3XX_idle_sg3: check-variables E310_SG3_IP $(BUILD_DIR)/E310_SG3_IDLE.dts
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$(call vivado_build,E310_SG3,$(DEFS) E310_IDLE_IMAGE=1 E310_SG3=1)
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$(call post_build,E310_SG3_IDLE)
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##E310_SG1: Build USRP E3XX (Speed Grade 1).
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E310_SG1 E310: check-variables E310_SG1_IP $(BUILD_DIR)/E310_SG1.dts
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$(call vivado_build,E310_SG1,$(DEFS) E310_SG1=1 $(if $(DRAM),ENABLE_DRAM=1,))
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$(call post_build,E310_SG1)
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##E310_SG3: Build USRP E3XX (Speed Grade 3).
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E310_SG3 E310_sg3: check-variables E310_SG3_IP $(BUILD_DIR)/E310_SG3.dts
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$(call vivado_build,E310_SG3,$(DEFS) E310_SG3=1 $(if $(DRAM),ENABLE_DRAM=1,))
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$(call post_build,E310_SG3)
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$(BUILD_DIR)/%.dts: dts/%.dts dts/*.dtsi
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${CC} -o $@ -E -I dts -nostdinc -undef -x assembler-with-cpp -D__DTS__ $<
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##
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##Other Make Targets (these should be called directly)
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##----------------------------------------------------
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##E310_SG1_IP: Build IP for E310_SG1 only. Use the -j option to build multiple IP blocks simultaneously.
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E310_SG1_IP:
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+$(call vivado_ip,E310_SG1,E310_SG1=1)
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##E310_SG3_IP: Build IP for E310_SG3 only. Use the -j option to build multiple IP blocks simultaneously.
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E310_SG3_IP:
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+$(call vivado_ip,E310_SG3,E310_SG3=1)
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clean: ##Clean up all target build outputs.
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@echo "Cleaning targets..."
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@rm -rf $(BUILD_BASE_DIR)/build-E3* $(BUILD_BASE_DIR)/build-usrp* $(BUILD_DIR)
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@rm -rf $(BUILD_OUTPUT_DIR)
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cleanall: ##Clean up all target and ip build outputs.
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@echo "Cleaning targets and IP..."
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@rm -rf build-ip
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@rm -rf $(BUILD_BASE_DIR)/build-* $(BUILD_DIR)
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@rm -rf $(BUILD_OUTPUT_DIR)
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help: ##Show this help message.
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@grep -h "##" Makefile | grep -v "\"##\"" | sed -e 's/\\$$//' | sed -e 's/##//'
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##
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##Supported Options
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##-----------------
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##DRAM=1 Include DDR3 SDRAM memory controller IP in the FPGA build.
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## Note: The RFNoC image core must also be configured to use DRAM.
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##GUI=1 Launch the build in the Vivado GUI.
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##PROJECT=1 Save Vivado project file, otherwise it's created in memory.
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##CHECK=1 Launch the syntax checker instead of building a bitfile.
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##IP_ONLY=1 Launch the build but stop after IP generation.
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##SYNTH=1 Launch the build but stop after synthesis.
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##BUILD_SEED=<N> Build seed to used to affect build results. (Default is 0)
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##TOP=<module> Specify a top module for syntax checking. (Default is the bitfile top)
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.PHONY: all clean cleanall help
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