Grant Meyerhoff 31ecc191a3 fpga: x440: correct crossbar replay port comments ...

Not a functional change. The comments for the replay block in the
crossbar_routes reflect a single replay block, but the FPGA image
actually has two replay blocks with half the number of ports as the
single block design.


Original-commit: 32efa102ce592ff16204b67b9aeb244e9589166e

2024-08-27 16:01:25 -05:00

export/x300/radio

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

lib

fpga/usrp3: Fix DC truncation bias by adding rounding to DDC chain.

2024-06-11 10:20:08 +02:00

sim

fpga: sim: Initialize test_status

2024-06-20 11:35:27 +02:00

tools

fpga: ci: remove color coding from FPGA bitfile name

2024-07-11 15:29:53 +02:00

top

fpga: x440: correct crossbar replay port comments

2024-08-27 16:01:25 -05:00

.gitignore

fpga: Add more spurious files to gitignore

2023-12-13 17:28:09 -06:00

build.py

fpga: Replace references to python -> python3

2023-12-05 15:43:08 -06:00

LICENSE.md

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

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