5cadf901c7
Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
128 lines
3.7 KiB
Verilog
128 lines
3.7 KiB
Verilog
//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ipass_present_controller
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//
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// Description:
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//
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// Translate the iPass present signals on FPGA to control port requests in
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// order to transfer them to the MB CPLD, which needs it for PCIe reset
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// generation.
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//
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`default_nettype none
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module ipass_present_controller (
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// Common ControlPort signals
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input wire ctrlport_clk,
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input wire ctrlport_rst,
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// ControlPort request
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output reg m_ctrlport_req_wr,
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output wire m_ctrlport_req_rd,
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output wire [19:0] m_ctrlport_req_addr,
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output wire [31:0] m_ctrlport_req_data,
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output wire [ 3:0] m_ctrlport_req_byte_en,
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// ControlPort response
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input wire m_ctrlport_resp_ack,
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input wire [ 1:0] m_ctrlport_resp_status,
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input wire [31:0] m_ctrlport_resp_data,
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// Configuration
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input wire enable,
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// Asynchronous ipass present signals
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input wire [ 1:0] ipass_present_n
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);
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`include "regmap/pl_cpld_regmap_utils.vh"
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`ifdef X440
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`include "cpld/regmap/x440/mb_cpld_pl_regmap_utils.vh"
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`else // Use X410 as the default variant for regmap.
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`include "cpld/regmap/x410/mb_cpld_pl_regmap_utils.vh"
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`endif
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`include "cpld/regmap/pl_cpld_base_regmap_utils.vh"
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`include "../../lib/rfnoc/core/ctrlport.vh"
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//-----------------------------------------------------------------------------
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// Transfer iPass signals to local clock domain
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//-----------------------------------------------------------------------------
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wire [1:0] ipass_present;
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wire [1:0] ipass_present_lcl;
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assign ipass_present = ~ipass_present_n;
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synchronizer #(
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.WIDTH (2),
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.STAGES (2),
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.INITIAL_VAL (0),
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.FALSE_PATH_TO_IN (1)
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) synchronizer_i (
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.clk (ctrlport_clk),
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.rst (ctrlport_rst),
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.in (ipass_present),
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.out (ipass_present_lcl)
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);
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//-----------------------------------------------------------------------------
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// Logic to wait for response after trigging request
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//-----------------------------------------------------------------------------
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reg transfer_in_progress = 1'b0;
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reg error_occurred = 1'b0;
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reg enable_delayed = 1'b0;
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reg [1:0] ipass_present_cached = 2'b0;
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// Rising-edge detection on enable signal
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wire activated;
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assign activated = enable & ~enable_delayed;
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always @(posedge ctrlport_clk) begin
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if (ctrlport_rst) begin
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m_ctrlport_req_wr <= 1'b0;
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transfer_in_progress <= 1'b0;
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enable_delayed <= 1'b0;
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error_occurred <= 1'b0;
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ipass_present_cached <= 2'b0;
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end else begin
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// Default assignment
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m_ctrlport_req_wr <= 1'b0;
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enable_delayed <= enable;
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// Issue new request on change if no request is pending
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if (((ipass_present_lcl != ipass_present_cached) || error_occurred || activated)
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&& ~transfer_in_progress && enable) begin
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transfer_in_progress <= 1'b1;
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m_ctrlport_req_wr <= 1'b1;
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ipass_present_cached <= ipass_present_lcl;
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end
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// Reset pending request
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if (m_ctrlport_resp_ack) begin
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transfer_in_progress <= 1'b0;
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error_occurred <= m_ctrlport_resp_status != CTRL_STS_OKAY;
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end
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end
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end
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//-----------------------------------------------------------------------------
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// Static ControlPort assignments
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//-----------------------------------------------------------------------------
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assign m_ctrlport_req_rd = 1'b0;
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assign m_ctrlport_req_byte_en = 4'b1111;
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assign m_ctrlport_req_addr = MB_CPLD + PL_REGISTERS + CABLE_PRESENT_REG;
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assign m_ctrlport_req_data = 32'b0 |
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(ipass_present_cached[0] << IPASS0_CABLE_PRESENT) |
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(ipass_present_cached[1] << IPASS1_CABLE_PRESENT);
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endmodule
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`default_nettype wire
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