miegl/b210-k7-fpga
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
2f5b331f300dc0dfb120e46e9fd49c1457abfb92
b210-k7-fpga/lib/fifo
T
History
Wade Fife c9d2c066f3 fpga: lib: Fix pass-through mode in axi_fifo 
A missing "else" after 6ea4e48 was causing two configurations to occur
at the same time for some values of SIZE.

This commit also sets the "space" and "occupied" outputs to 0 when in
pass-through mode.


Original-commit: 19b5c85b514e1c37238308e405108c69ecbddb7e
2025-04-08 12:26:02 -05:00
..
axi_demux4.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_demux8.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_demux.v
fpga: lib: Cleanup axi_demux module
2024-12-17 22:13:42 +01:00
axi_fifo16_to_fifo32.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fifo32_to_fifo16.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fifo32_to_fifo64.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fifo64_to_fifo32.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fifo_2clk.v
fpga: lib: add Intel MAX10 architecture for 2clk FIFO
2020-08-06 16:17:33 -05:00
axi_fifo_32_64_tb.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fifo_bram.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fifo_cascade.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fifo_flop2.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fifo_flop.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fifo_short.v
fpga: lib: Fix comments and indentation in axi_fifo_short.v
2020-08-04 15:40:08 -05:00
axi_fifo_tb.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fifo.v
fpga: lib: Fix pass-through mode in axi_fifo
2025-04-08 12:26:02 -05:00
axi_filter_mux4.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_loopback.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_mux4.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_mux8.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_mux_select.v
fpga: lib: Fix SWITCH_ON_LAST in axi_mux_select
2020-08-13 15:23:26 -05:00
axi_mux.v
fpga: lib: Clean up axi_mux
2021-10-28 23:15:41 -05:00
axi_packet_gate.v
fpga: lib: Fix axi_packet_gate RAM dib width
2020-06-29 13:41:15 -05:00
axis_fifo_monitor.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axis_strm_monitor.v
fpga: lib: Fix axis_strm_monitor parameters
2020-10-20 21:10:16 -05:00
fifo64_to_axi4lite.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile.srcs
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
shortfifo.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00